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1. 发明授权

US08976611B2 Asymmetric sensing amplifier, memory device and designing method 有权
标题翻译：非对称感测放大器，存储器件及设计方法
公开(公告)号：US08976611B2
公开(公告)日：2015-03-10
申请号：US13837614
申请日：2013-03-15
申请人： Jung-Ping Yang , Chia-En Huang , Fu-An Wu , Chih-Chieh Chiu , Cheng Hung Lee
发明人： Jung-Ping Yang , Chia-En Huang , Fu-An Wu , Chih-Chieh Chiu , Cheng Hung Lee
IPC分类号： G11C7/00 , G11C7/06 , G06F17/50 , G11C7/10 , G11C7/12 , G11C11/419
CPC分类号： G11C7/065 , G06F17/5063 , G06F17/5081 , G11C7/1048 , G11C7/12 , G11C11/419
摘要： A sensing amplifier for a memory device includes first and second nodes, an input device and an output device. The memory device includes first and second bit lines, and at least one memory cell coupled to the bit lines. The first and second nodes are coupled to the first and second bit lines, respectively. The input device is coupled to the first and second nodes and generates a first current pulling the first node toward a predetermined voltage in response to a first datum read out from the memory cell, and to generate a second current pulling the second node toward the predetermined voltage in response to a second datum read out from the memory cell. The output device is coupled to the first node to output the first or second datum read out from the memory cell. The first current is greater than the second current.
摘要翻译：用于存储器件的感测放大器包括第一和第二节点，输入设备和输出设备。存储器件包括第一和第二位线，以及耦合到位线的至少一个存储器单元。第一和第二节点分别耦合到第一和第二位线。输入设备耦合到第一和第二节点，并且响应于从存储器单元读出的第一数据产生第一电流将第一节点拉向预定电压，并且产生将第二节点拉向预定的第二电流的第二电流响应于从存储器单元读出的第二数据的电压。输出设备耦合到第一节点以输出从存储器单元读出的第一或第二数据。第一个电流大于第二个电流。

2. 发明授权

US07894220B2 Voltage generating circuit 有权
标题翻译：电压发生电路
公开(公告)号：US07894220B2
公开(公告)日：2011-02-22
申请号：US12057341
申请日：2008-03-27
申请人： Fu-An Wu
发明人： Fu-An Wu
IPC分类号： H02M3/18
CPC分类号： H02M3/07 , H02M3/073
摘要： A voltage generating circuit is provided, including a voltage output terminal, a ground terminal, a capacitor, a selector, a first switch, and a second switch. The capacitor is connected between a pump signal and the output of the selector. The selector is controlled by a first control signal and used to select the voltage source or the voltage output terminal to connect the capacitor. The first switch is controlled by a second control signal, and the second switch is controlled by a third control signal. When the first switch is turn-on, the voltage output terminal is connected to the ground terminal. When the second switch is turn-on, the voltage output terminal is connected to the voltage source.
摘要翻译：提供一种电压产生电路，包括电压输出端子，接地端子，电容器，选择器，第一开关和第二开关。电容器连接在泵信号和选择器的输出端之间。选择器由第一控制信号控制，用于选择电压源或电压输出端子以连接电容器。第一开关由第二控制信号控制，第二开关由第三控制信号控制。当第一个开关导通时，电压输出端子连接到接地端子。当第二开关导通时，电压输出端子连接到电压源。

3. 发明申请

US20090244940A1 VOLTAGE GENERATING CIRCUIT 有权
标题翻译：电压发生电路
公开(公告)号：US20090244940A1
公开(公告)日：2009-10-01
申请号：US12057341
申请日：2008-03-27
申请人： Fu-An Wu
发明人： Fu-An Wu
IPC分类号： H02M3/04
CPC分类号： H02M3/07 , H02M3/073
摘要： A voltage generating circuit is provided, including a voltage output terminal, a ground terminal, a capacitor, a selector, a first switch, and a second switch. The capacitor is connected between a pump signal and the output of the selector. The selector is controlled by a first control signal and used to select the voltage source or the voltage output terminal to connect the capacitor. The first switch is controlled by a second control signal, and the second switch is controlled by a third control signal. When the first switch is turn-on, the voltage output terminal is connected to the ground terminal. When the second switch is turn-on, the voltage output terminal is connected to the voltage source.
摘要翻译：提供一种电压产生电路，包括电压输出端子，接地端子，电容器，选择器，第一开关和第二开关。电容器连接在泵信号和选择器的输出端之间。选择器由第一控制信号控制，用于选择电压源或电压输出端子以连接电容器。第一开关由第二控制信号控制，第二开关由第三控制信号控制。当第一个开关导通时，电压输出端子连接到接地端子。当第二开关导通时，电压输出端子连接到电压源。

4. 发明申请

US20080008008A1 METHODS FOR PROGRAMMING AND READING NAND FLASH MEMORY DEVICE AND PAGE BUFFER PERFORMING THE SAME 有权
标题翻译：编程和读取NAND闪存存储器器件和执行其的页缓冲器的方法
公开(公告)号：US20080008008A1
公开(公告)日：2008-01-10
申请号：US11481022
申请日：2006-07-06
申请人： Chung Zen Chen , Jo Yu Wang , Fu An Wu
发明人： Chung Zen Chen , Jo Yu Wang , Fu An Wu
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/24 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5642
摘要： Methods for programming and reading a multi-level-cell NAND flash memory device having plural memory cells are disclosed to reduce the programming time and the reading time. The program method comprises the steps of: (a) programming the zero state memory cells, the first state memory cells, the second state memory cells and the third state memory cells to a zero state, (b) programming the second state memory cells from the zero state to a second state by switching the MSBs of the second state memory cells, and (c) programming the first state memory cells from the zero state to a first state by switching the LSBs of the first state memory cells and simultaneously programming the third state memory cells from the second state to a third state by switching the LSBs of the third state memory cells. The read method comprises the steps of: (d) reading the MSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by a first verify signal and a second verify signal, and (e) reading the LSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by the first verify signal and a third verify signal. A page buffer is also disclosed to perform the methods for programming and reading a multi-level-cell NAND flash memory device.
摘要翻译：公开了用于编程和读取具有多个存储器单元的多电平单元NAND闪速存储器件的方法，以减少编程时间和读取时间。程序方法包括以下步骤：（a）将零状态存储单元，第一状态存储单元，第二状态存储单元和第三状态存储单元编程为零状态，（b）将第二状态存储单元从通过切换第二状态存储单元的MSB来将零状态转换到第二状态，以及（c）通过切换第一状态存储单元的LSB并将第一状态存储单元的零状态编程为零，将第一状态存储单元从零状态编程为第一状态通过切换第三状态存储单元的LSB，从第二状态到第三状态的第三状态存储单元。读取方法包括以下步骤：（d）通过第一验证信号和第二验证信号读取零状态存储器单元，第一状态存储器单元，第二状态存储器单元和第三状态存储器单元的MSB，以及（e）通过第一验证信号和第三验证信号读取零状态存储器单元，第一状态存储器单元，第二状态存储器单元和第三状态存储器单元的LSB。还公开了一种页缓冲器来执行用于编程和读取多电平单元NAND闪存器件的方法。

5. 发明授权

US08659090B2 Resistive memory and methods for forming the same 有权
标题翻译：电阻记忆及其形成方法
公开(公告)号：US08659090B2
公开(公告)日：2014-02-25
申请号：US13335569
申请日：2011-12-22
申请人： Chia-En Huang , Wun-Jie Lin , Ling-Chang Hu , Hsiao-Lan Yang , Chih-Chieh Chiu , Wei-Shuo Kao , Hong-Chen Cheng , Fu-An Wu , Jung-Ping Yang , Cheng Hung Lee
发明人： Chia-En Huang , Wun-Jie Lin , Ling-Chang Hu , Hsiao-Lan Yang , Chih-Chieh Chiu , Wei-Shuo Kao , Hong-Chen Cheng , Fu-An Wu , Jung-Ping Yang , Cheng Hung Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.
摘要翻译：器件包括由半导体材料形成的有源区，有源区的表面处的栅极电介质和栅极电介质上的栅电极。第一源极/漏极区域和第二源极/漏极区域在栅电极的相对侧上。接触蚀刻停止层（CESL）位于第一和第二源极/漏极区域之上。层间电介质（ILD）包括与栅电极的顶表面基本上平齐的顶表面。第一接触插塞在第一源极/漏极区域上电连接。第二接触插塞在第二源极/漏极区域之上并对齐。第二接触插塞和第二源极/漏极区域通过第一CESL的一部分彼此隔开以形成电容器。

6. 发明申请

US20130161707A1 Resistive Memory and Methods for Forming the Same 有权
标题翻译：电阻记忆及其形成方法
公开(公告)号：US20130161707A1
公开(公告)日：2013-06-27
申请号：US13335569
申请日：2011-12-22
申请人： Chia-En Huang , Wun-Jie Lin , Ling-Chang Hu , Hsiao-Lan Yang , Chih-Chieh Chiu , Wei-Shuo Kao , Hong-Chen Cheng , Fu-An Wu , Jung-Ping Yang , Cheng Hung Lee
发明人： Chia-En Huang , Wun-Jie Lin , Ling-Chang Hu , Hsiao-Lan Yang , Chih-Chieh Chiu , Wei-Shuo Kao , Hong-Chen Cheng , Fu-An Wu , Jung-Ping Yang , Cheng Hung Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.
摘要翻译：器件包括由半导体材料形成的有源区，有源区的表面处的栅极电介质和栅极电介质上的栅电极。第一源极/漏极区域和第二源极/漏极区域在栅电极的相对侧上。接触蚀刻停止层（CESL）位于第一和第二源极/漏极区域之上。层间电介质（ILD）包括与栅电极的顶表面基本上平齐的顶表面。第一接触插塞在第一源极/漏极区域上电连接。第二接触插塞在第二源极/漏极区域之上并对齐。第二接触插塞和第二源极/漏极区域通过第一CESL的一部分彼此隔开以形成电容器。

7. 发明申请

US20140269110A1 ASYMMETRIC SENSING AMPLIFIER, MEMORY DEVICE AND DESIGNING METHOD 有权
标题翻译：不对称感应放大器，存储器件和设计方法
公开(公告)号：US20140269110A1
公开(公告)日：2014-09-18
申请号：US13837614
申请日：2013-03-15
申请人： Jung-Ping YANG , Chia-En HUANG , Fu-An WU , Chih-Chieh CHIU , Cheng Hung LEE
发明人： Jung-Ping YANG , Chia-En HUANG , Fu-An WU , Chih-Chieh CHIU , Cheng Hung LEE
IPC分类号： G11C7/06 , G06F17/50
CPC分类号： G11C7/065 , G06F17/5063 , G06F17/5081 , G11C7/1048 , G11C7/12 , G11C11/419
摘要： A sensing amplifier for a memory device includes first and second nodes, an input device and an output device. The memory device includes first and second bit lines, and at least one memory cell coupled to the bit lines. The first and second nodes are coupled to the first and second bit lines, respectively. The input device is coupled to the first and second nodes and generates a first current pulling the first node toward a predetermined voltage in response to a first datum read out from the memory cell, and to generate a second current pulling the second node toward the predetermined voltage in response to a second datum read out from the memory cell. The output device is coupled to the first node to output the first or second datum read out from the memory cell. The first current is greater than the second current.
摘要翻译：用于存储器件的感测放大器包括第一和第二节点，输入设备和输出设备。存储器件包括第一和第二位线，以及耦合到位线的至少一个存储器单元。第一和第二节点分别耦合到第一和第二位线。输入设备耦合到第一和第二节点，并且响应于从存储器单元读出的第一数据产生第一电流将第一节点拉向预定电压，并且产生将第二节点拉向预定的第二电流的第二电流响应于从存储器单元读出的第二数据的电压。输出设备耦合到第一节点以输出从存储器单元读出的第一或第二数据。第一个电流大于第二个电流。

8. 发明授权

US07359248B2 Methods for programming and reading NAND flash memory device and page buffer performing the same 有权
标题翻译：用于编程和读取NAND闪存器件和执行相同操作的页面缓冲器的方法
公开(公告)号：US07359248B2
公开(公告)日：2008-04-15
申请号：US11481022
申请日：2006-07-06
申请人： Chung Zen Chen , Jo Yu Wang , Fu An Wu
发明人： Chung Zen Chen , Jo Yu Wang , Fu An Wu
IPC分类号： G11C11/34
CPC分类号： G11C16/24 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5642
摘要： Methods for programming and reading a multi-level-cell NAND flash memory device having plural memory cells are disclosed to reduce the programming time and the reading time. The program method comprises the steps of: (a) programming the zero state memory cells, the first state memory cells, the second state memory cells and the third state memory cells to a zero state, (b) programming the second state memory cells from the zero state to a second state by switching the MSBs of the second state memory cells, and (c) programming the first state memory cells from the zero state to a first state by switching the LSBs of the first state memory cells and simultaneously programming the third state memory cells from the second state to a third state by switching the LSBs of the third state memory cells. The read method comprises the steps of: (d) reading the MSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by a first verify signal and a second verify signal, and (e) reading the LSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by the first verify signal and a third verify signal. A page buffer is also disclosed to perform the methods for programming and reading a multi-level-cell NAND flash memory device.
摘要翻译：公开了用于编程和读取具有多个存储器单元的多电平单元NAND闪速存储器件的方法，以减少编程时间和读取时间。程序方法包括以下步骤：（a）将零状态存储单元，第一状态存储单元，第二状态存储单元和第三状态存储单元编程为零状态，（b）将第二状态存储单元从通过切换第二状态存储单元的MSB来将零状态转换到第二状态，以及（c）通过切换第一状态存储单元的LSB并将第一状态存储单元的零状态编程为零，将第一状态存储单元从零状态编程为第一状态通过切换第三状态存储单元的LSB，从第二状态到第三状态的第三状态存储单元。读取方法包括以下步骤：（d）通过第一验证信号和第二验证信号读取零状态存储器单元，第一状态存储器单元，第二状态存储器单元和第三状态存储器单元的MSB，以及（e）通过第一验证信号和第三验证信号读取零状态存储器单元，第一状态存储器单元，第二状态存储器单元和第三状态存储器单元的LSB。还公开了一种页缓冲器来执行用于编程和读取多电平单元NAND闪存器件的方法。

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