专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090230409A1 UNDERFILL PROCESS FOR FLIP-CHIP LEDS 审中-公开
标题翻译： FLIP-CHIP LED的底层工艺
公开(公告)号：US20090230409A1
公开(公告)日：2009-09-17
申请号：US12050082
申请日：2008-03-17
申请人： Grigoriy Basin , Frederic Diana , Paul S. Martin , Dima Simonian
发明人： Grigoriy Basin , Frederic Diana , Paul S. Martin , Dima Simonian
IPC分类号： H01L33/00
CPC分类号： H01L33/54 , H01L24/97 , H01L33/0079 , H01L33/56 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00
摘要： An underfill technique for LEDs uses compression molding to simultaneously encapsulate an array of flip-chip LED dies mounted on a submount wafer. The molding process causes liquid underfill material (or a softened underfill material) to fill the gap between the LED dies and the submount wafer. The underfill material is then hardened, such as by curing. The cured underfill material over the top and sides of the LED dies is removed using microbead blasting. The exposed growth substrate is then removed from all the LED dies by laser lift-off, and the underfill supports the brittle epitaxial layers of each LED die during the lift-off process. The submount wafer is then singulated. This wafer-level processing of many LEDs simultaneously greatly reduces fabrication time, and a wide variety of materials may be used for the underfill since a wide range of viscosities is tolerable.
摘要翻译：用于LED的底部填充技术使用压缩成型来同时封装安装在底座晶片上的倒装芯片LED管芯阵列。成型工艺使液体底部填充材料（或软化的底部填充材料）填充LED管芯和底座晶片之间的间隙。然后将底部填充材料硬化，例如通过固化。使用微珠喷砂除去在LED管芯的顶部和侧面上固化的底部填充材料。然后通过激光剥离从所有LED管芯去除暴露的生长衬底，并且底部填充物在剥离过程中支持每个LED管芯的脆性外延层。然后将底座晶片分离。许多LED的晶片级处理同时大大减少了制造时间，并且可以使用各种各样的材料用于底部填充，因为宽范围的粘度是可以容忍的。

2. 发明授权

US09040332B2 Highly reflective coating on LED submount 有权
标题翻译： LED底座高反射涂层
公开(公告)号：US09040332B2
公开(公告)日：2015-05-26
申请号：US13878782
申请日：2011-10-07
申请人： Brendan Moran , Jeffrey Kmetec , Iain Black , Frederic Diana , Serge Laurent Rudaz , Li Zhang
发明人： Brendan Moran , Jeffrey Kmetec , Iain Black , Frederic Diana , Serge Laurent Rudaz , Li Zhang
IPC分类号： H01L33/08 , H01L33/60 , H01L33/50 , H01L33/62
CPC分类号： H01L33/60 , H01L33/50 , H01L33/62 , H01L2924/0002 , H01L2933/0066 , H01L2924/00
摘要： A submount for a light emitting stack includes a substrate and a metallization layer having circuit traces and a planar dielectric layer that fills regions between the circuit traces. The planar dielectric layer serves to minimize the amount of light lost/absorbed by the substrate and preferably reflects the internally reflected light back toward the desired light output element. To facilitate efficient manufacture, a dielectric paste is applied over the metallized layer, then planed to expose at least portions of the metal conductors for the subsequent coupling to the light emitting stack. Pedestal elements are preferably provided at select locations on the circuit traces to facilitate this coupling while allowing the remainder of the circuit traces to be covered with the dielectric layer.
摘要翻译：用于发光堆叠的基座包括衬底和具有电路迹线的金属化层和填充电路迹线之间的区域的平面介电层。平面介电层用于使由衬底损失/吸收的光的量最小化，并且优选地将内部反射的光反射回所需的光输出元件。为了促进有效的制造，将电介质浆料施加在金属化层上，然后设计成露出至少部分金属导体，以便随后与发光堆叠耦合。优选地，在电路迹线上的选择位置设置基座元件以促进该耦合，同时允许电路迹线的其余部分被电介质层覆盖。

3. 发明授权

US08273587B2 Underfill process for flip-chip LEDs 有权
标题翻译：倒装芯片LED的底部填充工艺
公开(公告)号：US08273587B2
公开(公告)日：2012-09-25
申请号：US13115475
申请日：2011-05-25
申请人： Grigoriy Basin , Frederic Diana , Paul S. Martin , Dima Simonian
发明人： Grigoriy Basin , Frederic Diana , Paul S. Martin , Dima Simonian
IPC分类号： H01L21/00
CPC分类号： H01L33/54 , H01L24/97 , H01L33/0079 , H01L33/56 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00
摘要： An underfill technique for LEDs uses compression molding to simultaneously encapsulate an array of flip-chip LED dies mounted on a submount wafer. The molding process causes liquid underfill material (or a softened underfill material) to fill the gap between the LED dies and the submount wafer. The underfill material is then hardened, such as by curing. The cured underfill material over the top and sides of the LED dies is removed using microbead blasting. The exposed growth substrate is then removed from all the LED dies by laser lift-off, and the underfill supports the brittle epitaxial layers of each LED die during the lift-off process. The submount wafer is then singulated. This wafer-level processing of many LEDs simultaneously greatly reduces fabrication time, and a wide variety of materials may be used for the underfill since a wide range of viscosities is tolerable.
摘要翻译：用于LED的底部填充技术使用压缩成型来同时封装安装在底座晶片上的倒装芯片LED管芯阵列。成型工艺使液体底部填充材料（或软化的底部填充材料）填充LED管芯和底座晶片之间的间隙。然后将底部填充材料硬化，例如通过固化。使用微珠喷砂除去在LED管芯的顶部和侧面上固化的底部填充材料。然后通过激光剥离从所有LED管芯去除暴露的生长衬底，并且底部填充物在剥离过程中支持每个LED管芯的脆性外延层。然后将底座晶片分离。许多LED的晶片级处理同时大大减少了制造时间，并且可以使用各种各样的材料用于底部填充，因为宽范围的粘度是可以容忍的。

4. 发明申请

US20050158988A1 Fabrication method for arranging ultra-fine particles 有权
标题翻译：用于排列超细颗粒的制造方法
公开(公告)号：US20050158988A1
公开(公告)日：2005-07-21
申请号：US10759589
申请日：2004-01-15
申请人： Seung-Heon Lee , Frederic Diana , Antonio Badolato , Pierre Petroff , Edward Kramer
发明人： Seung-Heon Lee , Frederic Diana , Antonio Badolato , Pierre Petroff , Edward Kramer
IPC分类号： G11B5/706 , H01F1/00 , H01F1/153 , H01L21/4763
CPC分类号： B82Y30/00 , B82Y10/00 , B82Y25/00 , B82Y40/00 , G11B5/706 , H01F1/009 , H01F1/15316
摘要： A method and resultant device, in which metal nanoparticles are self-assembled into two-dimensional lattices. A periodic hole pattern (wells) is fabricated on a photoresist substrate, the wells having an aspect ratio of less than 0.37. The nanoparticles are synthesized within inverse micelles of a polymer, preferably a block copolymer, and are self-assembled onto the photoresist nanopatterns. The nanoparticles are selectively positioned in the holes due to the capillary forces related to the pattern geometry, with a controllable number of particles per lattice point.
摘要翻译：金属纳米粒子自组装成二维晶格的方法和结果器件。在光致抗蚀剂基底上制造周期性孔图案（孔），孔的纵横比小于0.37。纳米颗粒在聚合物的反胶束中合成，优选嵌段共聚物，并且自组装到光致抗蚀剂纳米图案上。由于与图案几何形状相关的毛细力，纳米颗粒被选择性地定位在孔中，每个晶格点具有可控数量的颗粒。

5. 发明申请

US20130248913A1 HIGHLY REFLECTIVE COATING ON LED SUBMOUNT 有权
标题翻译： LED底座上的高反射涂层
公开(公告)号：US20130248913A1
公开(公告)日：2013-09-26
申请号：US13878782
申请日：2011-10-07
申请人： Brendan Moran , Jeffrey Kmetec , Iain Black , Frederic Diana , Serge Laurent Rudaz , Li Zhang
发明人： Brendan Moran , Jeffrey Kmetec , Iain Black , Frederic Diana , Serge Laurent Rudaz , Li Zhang
IPC分类号： H01L33/60 , H01L33/50
CPC分类号： H01L33/60 , H01L33/50 , H01L33/62 , H01L2924/0002 , H01L2933/0066 , H01L2924/00
摘要： A submount for a light emitting stack includes a substrate and a metallization layer having circuit traces and a planar dielectric layer that fills regions between the circuit traces. The planar dielectric layer serves to minimize the amount of light lost/absorbed by the substrate and preferably reflects the internally reflected light back toward the desired light output element. To facilitate efficient manufacture, a dielectric paste is applied over the metallized layer, then planed to expose at least portions of the metal conductors for the subsequent coupling to the light emitting stack. Pedestal elements are preferably provided at select locations on the circuit traces to facilitate this coupling while allowing the remainder of the circuit traces to be covered with the dielectric layer.
摘要翻译：用于发光堆叠的基座包括衬底和具有电路迹线的金属化层和填充电路迹线之间的区域的平面介电层。平面介电层用于使由衬底损失/吸收的光的量最小化，并且优选地将内部反射的光反射回所需的光输出元件。为了促进有效的制造，将电介质浆料施加在金属化层上，然后设计成露出至少部分金属导体，以便随后与发光堆叠耦合。优选地，在电路迹线上的选择位置设置基座元件以促进该耦合，同时允许电路迹线的其余部分被电介质层覆盖。

6. 发明申请

US20110223696A1 UNDERFILL PROCESS FOR FLIP-CHIP LEDS 有权
标题翻译： FLIP-CHIP LED的底层工艺
公开(公告)号：US20110223696A1
公开(公告)日：2011-09-15
申请号：US13115475
申请日：2011-05-25
申请人： Grigoriy Basin , Frederic Diana , Paul S. Martin , Dima Simonian
发明人： Grigoriy Basin , Frederic Diana , Paul S. Martin , Dima Simonian
IPC分类号： H01L33/52
CPC分类号： H01L33/54 , H01L24/97 , H01L33/0079 , H01L33/56 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00
摘要： An underfill technique for LEDs uses compression molding to simultaneously encapsulate an array of flip-chip LED dies mounted on a submount wafer. The molding process causes liquid underfill material (or a softened underfill material) to fill the gap between the LED dies and the submount wafer. The underfill material is then hardened, such as by curing. The cured underfill material over the top and sides of the LED dies is removed using microbead blasting. The exposed growth substrate is then removed from all the LED dies by laser lift-off, and the underfill supports the brittle epitaxial layers of each LED die during the lift-off process. The submount wafer is then singulated. This wafer-level processing of many LEDs simultaneously greatly reduces fabrication time, and a wide variety of materials may be used for the underfill since a wide range of viscosities is tolerable.
摘要翻译：用于LED的底部填充技术使用压缩成型来同时封装安装在底座晶片上的倒装芯片LED管芯阵列。成型工艺使液体底部填充材料（或软化的底部填充材料）填充LED管芯和底座晶片之间的间隙。然后将底部填充材料硬化，例如通过固化。使用微珠喷砂除去在LED管芯的顶部和侧面上固化的底部填充材料。然后通过激光剥离从所有LED管芯去除暴露的生长衬底，并且底部填充物在剥离过程中支持每个LED管芯的脆性外延层。然后将底座晶片分离。许多LED的晶片级处理同时大大减少了制造时间，并且可以使用各种各样的材料用于底部填充，因为宽范围的粘度是可以容忍的。

7. 发明申请

US20070085100A1 Photonic structures for efficient light extraction and conversion in multi-color light emitting devices 有权
标题翻译：用于多色发光器件中高效光提取和转换的光子结构
公开(公告)号：US20070085100A1
公开(公告)日：2007-04-19
申请号：US11251365
申请日：2005-10-14
申请人： Frederic Diana , Aurelien David , Pierre Petroff , Claude Weisbuch
发明人： Frederic Diana , Aurelien David , Pierre Petroff , Claude Weisbuch
IPC分类号： H01L33/00
CPC分类号： H01L33/20 , B82Y20/00 , G02B2006/1213 , H01L33/502 , H01L2933/0083
摘要： A high efficiency light emitting diode (LED) comprised of a substrate, a buffer layer grown on the substrate (if such a layer is needed), a first active region comprising primary emitting species (PES) that are electrically-injected, a second active region comprising secondary emitting species (SES) that are optically-pumped by the light emitted from the PES, and photonic crystals, wherein the photonic crystals act as diffraction gratings to provide high light extraction efficiency, to provide efficient excitation of the SES, and/or to modulate the far-field emission pattern.
摘要翻译：一种高效率的发光二极管（LED），包括衬底，在衬底上生长的缓冲层（如果需要这样的一层），第一有源区包括被电注入的一次发射物质（PES），第二有源区包括由从PES发射的光被光泵浦的二次发射物质（SES）的区域和光子晶体，其中所述光子晶体用作衍射光栅以提供高的光提取效率，以提供SES的有效激发和/ 或调制远场发射模式。

8. 发明申请

US20060154466A1 Fabrication method for arranging ultra-fine particles 有权
公开(公告)号：US20060154466A1
公开(公告)日：2006-07-13
申请号：US11274916
申请日：2005-11-14
申请人： Seung-Heon Lee , Frederic Diana , Antonio Badolato , Pierre Petroff , Edward Kramer
发明人： Seung-Heon Lee , Frederic Diana , Antonio Badolato , Pierre Petroff , Edward Kramer
IPC分类号： H01L21/44
CPC分类号： B82Y30/00 , B82Y10/00 , B82Y25/00 , B82Y40/00 , G11B5/706 , H01F1/009 , H01F1/15316
摘要： A method and resultant device, in which metal nanoparticles are self-assembled into two-dimensional lattices. A periodic hole pattern (wells) is fabricated on a photoresist substrate, the wells having an aspect ratio of less than 0.37. The nanoparticles are synthesized within inverse micelles of a polymer, preferably a block copolymer, and are self-assembled onto the photoresist nanopatterns. The nanoparticles are selectively positioned in the holes due to the capillary forces related to the pattern geometry, with a controllable number of particles per lattice point.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式