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1. 发明申请

US20050036502A1 System and method for handling multicast traffic in a shared buffer switch core collapsing ingress VOQ's 审中-公开
标题翻译：用于处理共享缓冲区交换机内核组播流量的系统和方法，崩溃入口VOQ
公开(公告)号：US20050036502A1
公开(公告)日：2005-02-17
申请号：US10895159
申请日：2004-07-20
申请人： Alain Blanc , Rene Glaise , Francois Maut , Michel Poret
发明人： Alain Blanc , Rene Glaise , Francois Maut , Michel Poret
IPC分类号： H04L12/43 , H04L12/56
CPC分类号： H04L49/9036 , H04L49/201 , H04L49/3036 , H04L49/3045 , H04L49/90
摘要： A system and a method to avoid packet traffic congestion in a shared memory switch core, while dramatically reducing the amount of shared memory in the switch core and the associated egress buffers and handling unicast as well as multicast traffic. According to the invention, the virtual output queuing (VOQ) of all ingress adapters of a packet switch fabric are collapsed into its central switch core to allow an efficient flow control. The transmission of data packets from an ingress buffer to the switch core is subject to a mechanism of request/acknowledgment. Therefore, a packet is transmitted from a virtual output queue to the memory shared switch core only if the switch core can send it to the corresponding egress buffer. A token based mechanism allows the switch core to determine the egress buffer's level of occupation. Therefore, since the switch core knows the states of the input and output adapters, it is able to optimize packet switching and to avoid packet congestion. Furthermore, since a packet is admitted in the switch core only if it can be transmitted to the corresponding egress buffer, the shared memory is reduced.
摘要翻译：一种避免共享存储交换机核心中的数据包流量拥塞的系统和方法，同时显着减少交换机核心和相关联的出口缓冲区中的共享存储器的数量以及处理单播以及组播流量。根据本发明，分组交换结构的所有入口适配器的虚拟输出排队（VOQ）被折叠到其中央交换机核心中以允许有效的流控制。数据包从入口缓冲区传输到交换机核心受到请求/确认机制的约束。因此，只有当交换机核心才能将其发送到对应的出口缓冲区时，才将数据包从虚拟输出队列发送到存储器共享交换机内核。基于令牌的机制允许交换机核心确定出口缓冲区的占用水平。因此，由于交换机核心知道输入和输出适配器的状态，因此能够优化分组交换并避免分组拥塞。此外，由于分组只有在可以发送到对应的出口缓冲器的情况下才允许在交换机核心中，所以共享存储器被减少。

2. 发明申请

US20080013548A1 Data Packet Switch and Method of Operating Same 失效
标题翻译：数据包交换机和操作方法相同
公开(公告)号：US20080013548A1
公开(公告)日：2008-01-17
申请号：US11852661
申请日：2007-09-10
申请人： Rene Glaise , Alain Blanc , Francois Maut , Michel Poret
发明人： Rene Glaise , Alain Blanc , Francois Maut , Michel Poret
IPC分类号： H04L12/56
CPC分类号： H04L49/15 , H04L49/103 , H04L49/1523 , H04L49/201 , H04L49/253 , H04L49/90
摘要： A high speed data packet switch comprising input and output ports and a switch fabric to link each input port to each output port wherein each connection between input and output ports comprises a dynamic buffer memory for storing at least one data packet for a minimum specified storing time is disclosed. When a data packet is received through an input port, it is written in all individual dynamic memory buffers connected to this input port so as to have a copy of the incoming data packet ready to go through any output port to support unicast, multicast and broadcast traffic. Given the architecture of the data packet switch and its control algorithm, dynamic memory buffers neither need to be refreshed nor their contents have to be restored after reading.
摘要翻译：包括输入和输出端口的高速数据分组交换机以及将每个输入端口链接到每个输出端口的交换结构，其中输入和输出端口之间的每个连接包括动态缓冲存储器，用于存储至少一个数据分组用于最小指定的存储时间被披露。当通过输入端口接收到数据包时，它被写入连接到该输入端口的所有单独的动态存储器缓冲器中，以便具有输入数据包的副本准备通过任何输出端口来支持单播，多播和广播交通。给定数据包交换机的架构及其控制算法，动态内存缓冲区既不需要刷新，也不需要在读取后恢复其内容。

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