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1. 发明授权

US09275923B2 Band pass filter for 2.5D/3D integrated circuit applications 有权
标题翻译： 2.5D / 3D集成电路应用的带通滤波器
公开(公告)号：US09275923B2
公开(公告)日：2016-03-01
申请号：US13557457
申请日：2012-07-25
申请人： Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Shuo-Mao Chen , Der-Chyang Yeh
发明人： Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Shuo-Mao Chen , Der-Chyang Yeh
IPC分类号： H05K7/00 , H01L21/56 , H01L23/31 , H01L23/64 , H01L23/66 , H01L25/16 , H01L23/00
CPC分类号： H01L23/3128 , H01L23/642 , H01L23/66 , H01L24/24 , H01L24/82 , H01L25/16 , H01L2223/6627 , H01L2223/6672 , H01L2224/12105 , H01L2224/24195 , H01L2924/181 , H01L2924/19011 , H01L2924/00
摘要： Some embodiments relate to a device and method for a band pass filter with a reduced cost, area penalty, and manufacturing complexity relative to current solutions. An integrated passive device chip includes a plurality of capacitors embedded in a common molding compound along with a transceiver chip. The integrated passive device chip and the transceiver chip are also arranged within a polymer package. An ultra-thick metallization layer is disposed within the polymer package and configured to couple the integrated passive device chip to the transceiver chip. The ultra-thick metallization layer also forms a plurality of transmission lines, wherein the combined integrated passive device chip and transmission lines form a band pass filter with improved frequency response, noise immunity, and cost and area as compared to conventional solutions.
摘要翻译：一些实施例涉及一种带通滤波器的器件和方法，其具有相对于当前解决方案的降低的成本，面积损失和制造复杂性。集成的无源器件芯片包括嵌入在共同的模制化合物中的多个电容器以及收发器芯片。集成无源器件芯片和收发器芯片也布置在聚合物封装内。超厚金属化层设置在聚合物封装内并且被配置成将集成的无源器件芯片耦合到收发器芯片。超厚金属化层还形成多条传输线，其中与常规解决方案相比，组合的集成无源器件芯片和传输线形成具有改进的频率响应，抗噪声性以及成本和面积的带通滤波器。

2. 发明授权

US09086452B2 Three-dimensional integrated circuit and method for wireless information access thereof 有权
标题翻译：用于无线信息访问的三维集成电路及方法
公开(公告)号：US09086452B2
公开(公告)日：2015-07-21
申请号：US13572533
申请日：2012-08-10
申请人： Mill-Jer Wang , Chewn-Pu Jou , Ching-Nen Peng , Huan-Neng Chen , Hung-Chih Lin , Kuang Kai Yen , Hao Chen , Feng Wei Kuo , Ming-Chieh Liu , Tsung-Hsiung Li
发明人： Mill-Jer Wang , Chewn-Pu Jou , Ching-Nen Peng , Huan-Neng Chen , Hung-Chih Lin , Kuang Kai Yen , Hao Chen , Feng Wei Kuo , Ming-Chieh Liu , Tsung-Hsiung Li
IPC分类号： G01R31/28 , H01L23/02 , G06F17/50 , H01L23/00 , H01L25/065 , G01R31/302
CPC分类号： G01R31/2889 , G01R31/3025 , G06F17/5068 , H01L24/16 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06565 , H01L2225/06596 , H01L2924/15192 , H01L2924/15311
摘要： A three-dimensional integrated circuit (3DIC) and wireless information access methods thereof are provided. The proposed 3DIC includes a semiconductor structure, and a wireless power device (WPD) formed on the semiconductor structure for wirelessly receiving a power for operating a function selected from a group consisting of probing the semiconductor structure, testing the semiconductor structure and accessing a first information from the semiconductor structure.
摘要翻译：提供了三维集成电路（3DIC）及其无线信息访问方法。所提出的3DIC包括半导体结构和形成在半导体结构上的无线功率器件（WPD），用于无线地接收用于操作从包括探测半导体结构，测试半导体结构和访问第一信息的组中选择的功能的功率从半导体结构。

3. 发明授权

US08922055B2 Driving circuit and method for driving current-driven devices and electronic device applying the same 有权
标题翻译：用于驱动电流驱动装置的驱动电路和方法及其应用的电子装置
公开(公告)号：US08922055B2
公开(公告)日：2014-12-30
申请号：US13080650
申请日：2011-04-05
申请人： Feng-Wei Chien , Tsung-Hau Chang
发明人： Feng-Wei Chien , Tsung-Hau Chang
IPC分类号： H02J1/00 , H05B33/08
CPC分类号： H05B33/0815 , H05B33/0827 , Y10T307/406 , Y10T307/469 , Y10T307/865
摘要： Provided is a light emitting diode (LED) driving circuit for driving a plurality of LED groups. The LED driving circuit includes: a voltage converter, for converting an input voltage into an output voltage, the output voltage coupled to a respective first terminal of each of the LED groups; and a controller, coupled to the voltage converter for controlling the voltage converter, the controller including a plurality of output channel terminals respectively corresponding to a plurality of output channels, one or more of the output channels are enabled and one or more of the output channels are disabled. One or more of the output channel terminals corresponding to the one or more enabled output channels are coupled to second terminals of corresponding ones of the LED groups, and one or more of the output channel terminals corresponding to the one or more disabled output channels are coupled to a reference voltage.
摘要翻译：提供了用于驱动多个LED组的发光二极管（LED）驱动电路。 LED驱动电路包括：电压转换器，用于将输入电压转换为输出电压，输出电压耦合到每个LED组的相应第一端; 以及耦合到所述电压转换器以控制所述电压转换器的控制器，所述控制器包括分别对应于多个输出通道的多个输出通道端子，所述输出通道中的一个或多个被使能，以及一个或多个输出通道被禁用对应于一个或多个使能的输出通道的输出通道端子中的一个或多个耦合到对应的LED组的第二端子，并且与一个或多个禁用的输出通道对应的一个或多个输出通道端子被耦合到参考电压。

4. 发明授权

US08769476B2 Method of performing circuit simulation and generating circuit layout 有权
标题翻译：执行电路仿真和生成电路布局的方法
公开(公告)号：US08769476B2
公开(公告)日：2014-07-01
申请号：US13464401
申请日：2012-05-04
申请人： Hui Yu Lee , Feng Wei Kuo , Jui-Feng Kuan , Simon Yi-Hung Chen
发明人： Hui Yu Lee , Feng Wei Kuo , Jui-Feng Kuan , Simon Yi-Hung Chen
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method of generating a circuit layout of an integrated circuit includes generating layout geometry parameters for at least a predetermined portion of an original netlist of the integrated circuit. A consolidated netlist including information from the original netlist and the layout geometry parameters is generated. Then, the circuit layout is generated based on the consolidated netlist.
摘要翻译：一种产生集成电路的电路布局的方法包括为集成电路的原始网表的至少预定部分生成布局几何参数。生成包含原始网表信息和布局几何参数的综合网表。然后，基于综合网表生成电路布局。

5. 发明授权

US08643402B2 Phase frequency detector circuit 有权
标题翻译：相位检波电路
公开(公告)号：US08643402B2
公开(公告)日：2014-02-04
申请号：US13308274
申请日：2011-11-30
申请人： Yen-Jen Chen , I-Ting Lee , Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou
发明人： Yen-Jen Chen , I-Ting Lee , Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou
IPC分类号： H03D13/00 , H03D3/00
CPC分类号： H03D13/00 , H03D13/004 , H03L7/087 , H03L7/089 , H03L7/10
摘要： A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.
摘要翻译：相位频率检测器电路包括边缘检测器电路，多个相位频率检测器子电路和判定电路。边缘检测器电路被配置为接收第一输入信号和第二输入信号。判定电路被配置为基于边缘检测器电路的输出和多个相位频率检测器子电路的输出来检测盲状态是否退出。响应于判定电路的结果，多个相位频率检测器子电路的对应的频率检测器子电路被配置为提供用于确定第一输入信号和第二输入信号之间的相位差的信号。

6. 发明授权

US08621409B2 System and method for reducing layout-dependent effects 有权
标题翻译：减少与布局有关的影响的系统和方法
公开(公告)号：US08621409B2
公开(公告)日：2013-12-31
申请号：US13459288
申请日：2012-04-30
申请人： Hui Yu Lee , Feng Wei Kuo , Ching-Shun Yang , Yi-Kan Cheng , Jui-Feng Kuan
发明人： Hui Yu Lee , Feng Wei Kuo , Ching-Shun Yang , Yi-Kan Cheng , Jui-Feng Kuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool. A weight and a sensitivity of the at least one layout-dependent effect are calculated, and the first layout of the semiconductor circuit is adjusted based on the weight and the sensitivity to provide a second layout of the semiconductor circuit. The second layout is stored in a non-transient storage medium.
摘要翻译：一种方法包括从半导体电路的第一布局提取第一网表并基于第一网表估计与布局有关的效果数据。基于使用电子设计自动化工具的第一网表执行半导体电路的第一仿真，并且基于使用电子设计自动化工具的电路示意图来执行半导体电路的第二仿真。计算至少一个与布局相关的效果的重量和灵敏度，并且基于重量和灵敏度来调整半导体电路的第一布局以提供半导体电路的第二布局。第二布局存储在非瞬态存储介质中。

7. 发明申请

US20130328789A1 TOUCH DEVICE AND OPERATING METHOD THEREOF 审中-公开
标题翻译：触摸装置及其操作方法
公开(公告)号：US20130328789A1
公开(公告)日：2013-12-12
申请号：US13492428
申请日：2012-06-08
申请人： Jui-Ming Liu , Chung-Wen Chang , Feng-Wei Yang , Shen-Feng Tai
发明人： Jui-Ming Liu , Chung-Wen Chang , Feng-Wei Yang , Shen-Feng Tai
IPC分类号： G06F3/041
CPC分类号： G06F3/0416
摘要： A touch device and an operating method of the touch device are provided. The operating method includes following steps. A plurality of touch values of a touch panel are obtained. During a first frame period, the obtained touch values are stored in a first memory unit, and a touch point is calculated according to the touch values stored in a second memory unit. During a second frame period, the obtained touch values are stored in the second memory unit, and the touch point is calculated according to the touch values stored in the first memory unit.
摘要翻译：提供了触摸装置和触摸装置的操作方法。操作方法包括以下步骤。获得触摸面板的多个触摸值。在第一帧周期期间，将获得的触摸值存储在第一存储单元中，并且根据存储在第二存储单元中的触摸值来计算触摸点。在第二帧周期期间，获得的触摸值被存储在第二存储器单元中，并且根据存储在第一存储器单元中的触摸值来计算触摸点。

8. 发明申请

US20130320553A1 NOVEL BEAD FOR 2.5D/3D CHIP PACKAGING APPLICATION 有权
标题翻译： 2.5D / 3D芯片包装应用的新颖的珠子
公开(公告)号：US20130320553A1
公开(公告)日：2013-12-05
申请号：US13481974
申请日：2012-05-29
申请人： Feng Wei KUO , Huan-Neng CHEN , Chewn-Pu JOU , Der-Chyang YEH , Chuei-Tang WANG
发明人： Feng Wei KUO , Huan-Neng CHEN , Chewn-Pu JOU , Der-Chyang YEH , Chuei-Tang WANG
IPC分类号： H01L23/48
CPC分类号： H01L23/528 , H01L23/5227 , H01L23/552 , H01L2223/6616 , H01L2224/04105 , H01L2224/24137 , H01L2924/14 , H01L2924/15311 , H01L2924/18162
摘要： An integrated circuit package having a multilayer interposer has one or more metal wiring beads provided in the interposer, each of the one or more metal wiring beads has a convoluted wiring pattern that is formed in one of the multiple layers of wiring structures in the interposer, and two terminal end segments connected to the power lines in the integrated circuit package, wherein the one or more metal wiring beads operate as power noise filters.
摘要翻译：具有多层插入器的集成电路封装具有设置在插入件中的一个或多个金属布线珠，所述一个或多个金属布线珠中的每一个具有形成在所述插入件中的所述多层布线结构中的一层中的卷曲布线图案，以及连接到集成电路封装中的电力线的两个终端段，其中所述一个或多个金属布线珠作为功率噪声滤波器起作用。

9. 发明申请

US20130298091A1 METHOD OF PERFORMING CIRCUIT SIMULATION AND GENERATING CIRCUIT LAYOUT 有权
标题翻译：执行电路仿真和生成电路布局的方法
公开(公告)号：US20130298091A1
公开(公告)日：2013-11-07
申请号：US13464401
申请日：2012-05-04
申请人： Hui Yu LEE , Feng Wei KUO , Jui-Feng KUAN , Simon Yi-Hung CHEN
发明人： Hui Yu LEE , Feng Wei KUO , Jui-Feng KUAN , Simon Yi-Hung CHEN
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method of generating a circuit layout of an integrated circuit includes generating layout geometry parameters for at least a predetermined portion of an original netlist of the integrated circuit. A consolidated netlist including information from the original netlist and the layout geometry parameters is generated. Then, the circuit layout is generated based on the consolidated netlist.
摘要翻译：一种产生集成电路的电路布局的方法包括为集成电路的原始网表的至少预定部分生成布局几何参数。生成包含原始网表信息和布局几何参数的综合网表。然后，基于综合网表生成电路布局。

10. 发明申请

US20130234305A1 3D TRANSMISSION LINES FOR SEMICONDUCTORS 有权
标题翻译：用于半导体的3D传输线
公开(公告)号：US20130234305A1
公开(公告)日：2013-09-12
申请号：US13415906
申请日：2012-03-09
申请人： Yu-Ling LIN , Hsiao-Tsung YEN , Feng Wei KUO , Ho-Hsiang CHEN , Chin-Wei KUO
发明人： Yu-Ling LIN , Hsiao-Tsung YEN , Feng Wei KUO , Ho-Hsiang CHEN , Chin-Wei KUO
IPC分类号： H01L23/58 , H01L21/28
CPC分类号： H01L23/60 , H01L23/5222 , H01L23/5225 , H01L23/66 , H01L25/0657 , H01L2223/6627 , H01L2225/06527 , H01L2225/06537 , H01L2924/0002 , H01L2924/00
摘要： A transmission line structure for semiconductor RF and wireless circuits, and method for forming the same. The transmission line structure includes embodiments having a first die including a first substrate, a first insulating layer, and a ground plane, and a second die including a second substrate, a second insulating layer, and a signal transmission line. The second die may be positioned above and spaced apart from the first die. An underfill is disposed between the ground plane of the first die and the signal transmission line of the second die. Collectively, the ground plane and transmission line of the first and second die and underfill forms a compact transmission line structure. In some embodiments, the transmission line structure may be used for microwave applications.
摘要翻译：用于半导体RF和无线电路的传输线结构及其形成方法。传输线结构包括具有包括第一衬底，第一绝缘层和接地平面的第一裸片的实施例，以及包括第二衬底，第二绝缘层和信号传输线的第二裸片。第二管芯可以位于第一管芯的上方并与之隔开。在第一管芯的接地面和第二管芯的信号传输线之间设置底部填充物。总的来说，第一和第二模具和底部填充物的接地平面和传输线形成紧凑的传输线结构。在一些实施例中，传输线结构可用于微波应用。

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