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1. 发明申请

US20160013186A1 SEMICONDUCTOR DEVICE HAVING FIN-TYPE FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有微型场效应晶体管的半导体器件及其制造方法
公开(公告)号：US20160013186A1
公开(公告)日：2016-01-14
申请号：US14330306
申请日：2014-07-14
申请人： Dong-Il Bae , Kang-Ill Seo
发明人： Dong-Il Bae , Kang-Ill Seo
IPC分类号： H01L27/088 , H01L29/161 , H01L21/3105 , H01L29/66 , H01L21/8234 , H01L29/78 , H01L21/02
CPC分类号： H01L27/0886 , H01L21/31053 , H01L21/823431 , H01L29/0673 , H01L29/0847 , H01L29/161 , H01L29/42364 , H01L29/42392 , H01L29/66439 , H01L29/6681 , H01L29/775 , H01L29/7851 , H01L29/78696
摘要： A semiconductor device includes a first fin structure disposed on a substrate. The first fin structure extends in a first direction. A first sacrificial layer pattern is disposed on the first fin structure. The first sacrificial layer pattern includes a left portion and a right portion arranged in the first direction. A dielectric layer pattern is disposed on the first fin structure and interposed between the left and right portions of the first sacrificial layer pattern. A first active layer pattern extending in the first direction is disposed on the first sacrificial layer pattern and the dielectric layer pattern. A first gate electrode structure is disposed on a portion of the first active layer pattern. The portion of the first active layer is disposed on the dielectric layer pattern. The first gate electrode structure extends in a second direction crossing the first direction.
摘要翻译：半导体器件包括设置在衬底上的第一鳍结构。第一翅片结构沿第一方向延伸。第一牺牲层图案设置在第一鳍结构上。第一牺牲层图案包括沿第一方向布置的左部分和右部分。电介质层图案设置在第一鳍片结构上并且介于第一牺牲层图案的左右部分之间。沿第一方向延伸的第一有源层图案设置在第一牺牲层图案和介电层图案上。第一栅电极结构设置在第一有源层图案的一部分上。第一有源层的部分设置在电介质层图案上。第一栅电极结构沿与第一方向交叉的第二方向延伸。

2. 发明授权

US08253201B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US08253201B2
公开(公告)日：2012-08-28
申请号：US12458800
申请日：2009-07-23
申请人： Dong-Il Bae
发明人： Dong-Il Bae
IPC分类号： H01L27/12
CPC分类号： H01L27/11507 , H01L21/84 , H01L27/10802 , H01L27/1203 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A memory device includes a MOS transistor including a gate structure, a first impurity region, a second impurity region, and a floating body positioned between the first and the second impurity regions on a semiconductor substrate including a buried oxide layer. The memory device includes a charge storage structure of the non-volatile memory device electrically connected to the second impurity region of the MOS transistor.
摘要翻译：存储器件包括在包括掩埋氧化物层的半导体衬底上的包括栅极结构，第一杂质区，第二杂质区和位于第一和第二杂质区之间的浮体的MOS晶体管。存储装置包括与MOS晶体管的第二杂质区电连接的非易失性存储器件的电荷存储结构。

3. 发明申请

US20100019299A1 Memory device 有权
标题翻译：内存设备
公开(公告)号：US20100019299A1
公开(公告)日：2010-01-28
申请号：US12458800
申请日：2009-07-23
申请人： Dong-Il Bae
发明人： Dong-Il Bae
IPC分类号： H01L27/105
CPC分类号： H01L27/11507 , H01L21/84 , H01L27/10802 , H01L27/1203 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A memory device includes a MOS transistor including a gate structure, a first impurity region, a second impurity region, and a floating body positioned between the first and the second impurity regions on a semiconductor substrate including a buried oxide layer. The memory device includes a charge storage structure of the non-volatile memory device electrically connected to the second impurity region of the MOS transistor.
摘要翻译：存储器件包括在包括掩埋氧化物层的半导体衬底上的包括栅极结构，第一杂质区，第二杂质区和位于第一和第二杂质区之间的浮体的MOS晶体管。存储装置包括与MOS晶体管的第二杂质区电连接的非易失性存储器件的电荷存储结构。

4. 发明申请

US20160013309A1 SEMICONDUCTOR DEVICE HAVING GATE-ALL-AROUND TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有门极绕晶体管的半导体器件及其制造方法
公开(公告)号：US20160013309A1
公开(公告)日：2016-01-14
申请号：US14330305
申请日：2014-07-14
申请人： DONG-IL BAE , KANG-ILL SEO
发明人： DONG-IL BAE , KANG-ILL SEO
IPC分类号： H01L29/78 , H01L29/66 , H01L27/11 , H01L27/088 , H01L27/092
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L27/0886 , H01L27/092 , H01L27/0924 , H01L27/1104 , H01L27/1116 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/78618 , H01L29/78654 , H01L29/78684 , H01L29/78696 , H01L2029/7858
摘要： A semiconductor device includes a fin structure disposed on a substrate, a sacrificial layer pattern disposed on the fin structure, an active layer pattern disposed on the sacrificial layer pattern, and a gate dielectric layer and a gate electrode layer extending through the sacrificial layer pattern and surrounding a portion of the active layer pattern.
摘要翻译：半导体器件包括设置在衬底上的翅片结构，设置在鳍结构上的牺牲层图案，设置在牺牲层图案上的有源层图案，以及延伸穿过牺牲层图案的栅极电介质层和栅电极层，以及围绕有源层图案的一部分。

5. 发明授权

US07864595B2 Nonvolatile memory cell, nonvolatile memory device, and method of programming the nonvolatile memory device 有权
标题翻译：非易失性存储单元，非易失性存储器件以及非易失性存储器件的编程方法
公开(公告)号：US07864595B2
公开(公告)日：2011-01-04
申请号：US12367993
申请日：2009-02-09
申请人： Dong-Il Bae
发明人： Dong-Il Bae
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10
摘要： A method of programming a nonvolatile memory device. The method may include pre-programming one memory cell among a plurality of memory cells by storing data in a first data storage layer using a first program voltage applied to one word line corresponding to the one memory cell among the plurality of memory cells; and while pre-programming other memory cells among the plurality of memory cells, background-programming the pre-programmed memory cell by moving the stored data to a second data storage layer using a second program voltage that is higher than the first program voltage applied to the word line of the pre-programmed memory cell.
摘要翻译：一种编程非易失性存储器件的方法。该方法可以包括通过使用施加到多个存储单元中对应于一个存储单元的一个字线的第一编程电压将数据存储在第一数据存储层中来预编程多个存储器单元中的一个存储单元; 并且在多个存储单元之间对其它存储单元进行预编程的同时，通过使用高于施加到第一编程电压的第二编程电压将存储的数据移动到第二数据存储层来对该预编程的存储单元进行背景编程预编程存储单元的字线。

6. 发明授权

US07504295B2 Methods for fabricating dynamic random access memory cells having laterally offset storage nodes 失效
标题翻译：制造具有横向偏移存储节点的动态随机存取存储器单元的方法
公开(公告)号：US07504295B2
公开(公告)日：2009-03-17
申请号：US11470011
申请日：2006-09-05
申请人： Sang-hyeon Lee , Dong-il Bae
发明人： Sang-hyeon Lee , Dong-il Bae
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/8244
CPC分类号： H01L27/10852 , H01L21/76895 , H01L27/0207 , H01L28/60
摘要： DRAM cells include a common drain region in an integrated circuit substrate and first and second source regions in the integrated circuit substrate, a respective one of which is laterally offset from the common drain region along respective first and second opposite directions. First and second storage nodes are provided on the integrated circuit substrate, a respective one of which is electrically connected to a respective one of the first and second source regions. The first and second storage nodes are laterally offset from the respective first and second source regions along the first direction.
摘要翻译： DRAM单元包括集成电路衬底中的公共漏极区域和集成电路衬底中的第一和第二源极区域，其相应的一个沿相应的第一和第二相反方向从公共漏极区域侧向偏移。第一和第二存储节点设置在集成电路基板上，其相应的一个电连接到第一和第二源极区域中的相应一个。第一和第二存储节点沿着第一方向从相应的第一和第二源区域侧向偏移。

7. 发明申请

US20070026603A1 Methods for Fabricating Dynamic Random Access Memory Cells Having Laterally Offset Storage Nodes 失效
标题翻译：用于制造具有侧向偏移存储节点的动态随机存取存储器单元的方法
公开(公告)号：US20070026603A1
公开(公告)日：2007-02-01
申请号：US11470011
申请日：2006-09-05
申请人： Sang-hyeon Lee , Dong-il Bae
发明人： Sang-hyeon Lee , Dong-il Bae
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852 , H01L21/76895 , H01L27/0207 , H01L28/60
摘要： DRAM cells include a common drain region in an integrated circuit substrate and first and second source regions in the integrated circuit substrate, a respective one of which is laterally offset from the common drain region along respective first and second opposite directions. First and second storage nodes are provided on the integrated circuit substrate, a respective one of which is electrically connected to a respective one of the first and second source regions. The first and second storage nodes are laterally offset from the respective first and second source regions along the first direction.
摘要翻译： DRAM单元包括集成电路衬底中的公共漏极区域和集成电路衬底中的第一和第二源极区域，其相应的一个沿相应的第一和第二相反方向从公共漏极区域侧向偏移。第一和第二存储节点设置在集成电路基板上，其相应的一个电连接到第一和第二源极区域中的相应一个。第一和第二存储节点沿着第一方向从相应的第一和第二源区域侧向偏移。

8. 发明授权

US06730956B2 Method for manufacturing the storage node of a capacitor of a semiconductor device and a storage node manufactured by the method 失效
标题翻译：用于制造半导体器件的电容器的存储节点的方法和通过该方法制造的存储节点
公开(公告)号：US06730956B2
公开(公告)日：2004-05-04
申请号：US10329488
申请日：2002-12-27
申请人： Dong-il Bae , Dong-won Shin , Sang-hyeon Lee
发明人： Dong-il Bae , Dong-won Shin , Sang-hyeon Lee
IPC分类号： H01L27108
CPC分类号： H01L28/91 , H01L27/10852
摘要： Methods for manufacturing a storage node of a capacitor of a semiconductor device and a storage node manufactured by these methods are provided. An exemplary method for manufacturing a storage node of a capacitor of a semiconductor device includes forming a mold layer on a semiconductor substrate, forming a mold for the storage node by patterning the mold layer by a photolithography process, introducing a photomask which includes a plurality of light transmitting patterns separated from each other and which define the region to be occupied by the storage node, and forming a storage node that has the shape formed by the mold. The photolithography process is performed with the occurrence of a pattern bridge phenomenon, e.g., the transferred light transmitting patterns are connected to each other in a pattern transferred from the light transmitting patterns to the mold.
摘要翻译：提供了通过这些方法制造半导体器件的电容器的存储节点和存储节点的方法。用于制造半导体器件的电容器的存储节点的示例性方法包括在半导体衬底上形成模具层，通过光刻工艺对模具层进行图案化形成用于存储节点的模具，引入包括多个光传输图案彼此分离并且限定要由存储节点占据的区域，以及形成具有由模具形成的形状的存储节点。光刻工艺是在出现图形桥现象的情况下进行的，例如，转印的光透射图案以从透光图案转印到模具的图案彼此连接。

9. 发明申请

US20100014358A1 NONVOLATILE MEMORY CELL, NONVOLATILE MEMORY DEVICE, AND METHOD OF PROGRAMMING THE NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器单元，非易失性存储器件以及非易失性存储器件的编程方法
公开(公告)号：US20100014358A1
公开(公告)日：2010-01-21
申请号：US12367993
申请日：2009-02-09
申请人： Dong-Il BAE
发明人： Dong-Il BAE
IPC分类号： G11C16/06
CPC分类号： G11C16/10
摘要： A method of programming a nonvolatile memory device. The method may include pre-programming one memory cell among a plurality of memory cells by storing data in a first data storage layer using a first program voltage applied to one word line corresponding to the one memory cell among the plurality of memory cells; and while pre-programming other memory cells among the plurality of memory cells, background-programming the pre-programmed memory cell by moving the stored data to a second data storage layer using a second program voltage that is higher than the first program voltage applied to the word line of the pre-programmed memory cell.
摘要翻译：一种编程非易失性存储器件的方法。该方法可以包括通过使用施加到多个存储单元中对应于一个存储单元的一个字线的第一编程电压将数据存储在第一数据存储层中来预编程多个存储器单元中的一个存储单元; 并且在多个存储单元之间对其它存储单元进行预编程的同时，通过使用高于施加到第一编程电压的第二编程电压将存储的数据移动到第二数据存储层来对该预编程的存储单元进行背景编程预编程存储单元的字线。

10. 发明申请

US20100008139A1 Memory devices having volatile and non-volatile memory characteristics and methods of operating the same 有权
标题翻译：具有易失性和非易失性存储器特性的存储器件及其操作方法
公开(公告)号：US20100008139A1
公开(公告)日：2010-01-14
申请号：US12458299
申请日：2009-07-08
申请人： Dong-Il Bae
发明人： Dong-Il Bae
IPC分类号： G11C16/04 , G11C14/00 , G11C7/00 , G11C7/06
CPC分类号： G11C11/404 , G11C11/005 , G11C14/0018 , G11C16/0475 , G11C2211/4016
摘要： Multi-bit semiconductor memory devices having both volatile and nonvolatile memory characteristics and methods of operating the same are disclosed, the semiconductor memory device including a floating body on an upper region of a substrate, a gate electrode on the floating body and electrically insulated from the floating body, source and drain regions on the substrate adjacent to the gate electrode and a charge trap layer between the floating body and the gate electrode, where first bit data is written in one of the charge trap layer and the floating body, and second bit data is written in one of the charge trap layer and the floating body in which first bit data is not written.
摘要翻译：公开了具有易失性和非易失性存储器特性的两位半导体存储器件及其操作方法，该半导体存储器件包括在衬底的上部区域上的浮体，浮动体上的栅电极，与栅电极相邻的衬底上的浮体，源极和漏极区域以及浮动体和栅电极之间的电荷陷阱层，其中第一位数据被写入电荷陷阱层和浮体之一，以及第二位数据被写入电荷陷阱层和不写第一位数据的浮动体之一。

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