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1. 发明申请

US20140035164A1 Semiconductor Device and Method of Fabricating the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140035164A1
公开(公告)日：2014-02-06
申请号：US14052691
申请日：2013-10-11
申请人： Kwang-jin Moon , Byung-lyul Park , Dong-chan Lim , Deok-young Jung , Gil-heyun Choi , Dae-lok Bae , Pil-kyu Kang
发明人： Kwang-jin Moon , Byung-lyul Park , Dong-chan Lim , Deok-young Jung , Gil-heyun Choi , Dae-lok Bae , Pil-kyu Kang
IPC分类号： H01L23/522
CPC分类号： H01L23/5226 , H01L21/76898 , H01L23/481 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a via structure having a top surface with a planar portion and a protrusion portion that is surrounded by the planar portion, and includes a conductive structure including a plurality of conductive lines contacting at least a part of the top surface of the via structure.
摘要翻译：半导体器件包括具有平面部分的顶表面和由平面部分包围的突出部分的通孔结构，并且包括导电结构，该导电结构包括与通孔的顶表面的至少一部分接触的多条导线结构体。

2. 发明申请

US20130187287A1 Semiconductor Device and Method of Fabricating the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130187287A1
公开(公告)日：2013-07-25
申请号：US13627790
申请日：2012-09-26
申请人： Byung-lyul Park , Gil-Heyun Choi , Suk-Chul Bang , Kwang-Jin Moon , Dong-Chan Lim , Deok-Young Jung
发明人： Byung-lyul Park , Gil-Heyun Choi , Suk-Chul Bang , Kwang-Jin Moon , Dong-Chan Lim , Deok-Young Jung
IPC分类号： H01L23/498
CPC分类号： H01L21/76898 , H01L21/76801 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565
摘要： A semiconductor device includes a circuit pattern over a first surface of a substrate, an insulating interlayer covering the circuit pattern, a TSV structure filling a via hole through the insulating interlayer and the substrate, an insulation layer structure on an inner wall of the via hole and on a top surface of the insulating interlayer, a buffer layer on the TSV structure and the insulation layer structure, a conductive structure through the insulation layer structure and a portion of the insulating interlayer to be electrically connected to the circuit pattern, a contact pad onto a bottom of the TSV structure, and a protective layer structure on a second surface the substrate to surround the contact pad.
摘要翻译：半导体器件包括在衬底的第一表面上的电路图案，覆盖电路图案的绝缘夹层，填充通过绝缘夹层和衬底的通孔的TSV结构，在通孔的内壁上的绝缘层结构并且在绝缘中间层的上表面上，具有TSV结构和绝缘层结构的缓冲层，通过绝缘层结构的导电结构和电连接到电路图案的绝缘夹层的一部分，接触垫到TSV结构的底部，以及在第二表面上的保护层结构，以包围接触垫。

3. 发明申请

US20130119547A1 INTEGRATED CIRCUIT DEVICE INCLUDING THROUGH-SILICON VIA STRUCTURE HAVING OFFSET INTERFACE 有权
标题翻译：集成电路设备，通过具有偏移接口的结构，包括硅
公开(公告)号：US20130119547A1
公开(公告)日：2013-05-16
申请号：US13603978
申请日：2012-09-05
申请人： Su-kyoung Kim , Gil-heyun Choi , Byung-Iyul Park , Kwang-jin Moon , Kun-sang Park , Dong-chan Lim , Do-sun Lee
发明人： Su-kyoung Kim , Gil-heyun Choi , Byung-Iyul Park , Kwang-jin Moon , Kun-sang Park , Dong-chan Lim , Do-sun Lee
IPC分类号： H01L23/532 , H01L23/498
CPC分类号： H01L21/76898 , H01L23/481 , H01L23/49827 , H01L25/0657 , H01L2224/16 , H01L2924/13091 , H01L2924/00
摘要： An integrated circuit device includes a substrate through which a first through-hole extends, and an interlayer insulating film on the substrate, the interlayer insulating film having a second through-hole communicating with the first through-hole. A Through-Silicon Via (TSV) structure is provided in the first through-hole and the second through-hole. The TSV structure extends to pass through the substrate and the interlayer insulating film. The TSV structure comprises a first through-electrode portion having a top surface located in the first through-hole, and a second through-electrode portion having a bottom surface contacting with the top surface of the first through-electrode portion and extending from the bottom surface to at least the second through-hole. Related fabrication methods are also described.
摘要翻译：集成电路器件包括：第一通孔延伸穿过的衬底和衬底上的层间绝缘膜，所述层间绝缘膜具有与第一通孔连通的第二通孔。在第一通孔和第二通孔中设置有硅通孔（TSV）结构。 TSV结构延伸穿过衬底和层间绝缘膜。 TSV结构包括具有位于第一通孔中的顶表面的第一通电极部分和具有与第一贯穿电极部分的顶表面接触并从底部延伸的底表面的第二通电极部分表面至少到第二通孔。还描述了相关的制造方法。

4. 发明授权

US08390120B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08390120B2
公开(公告)日：2013-03-05
申请号：US12913748
申请日：2010-10-27
申请人： Kwang-Jin Moon , Pil-Kyu Kang , Dae-Lok Bae , Gil-Heyun Choi , Byung-Lyul Park , Dong-Chan Lim , Deok-Young Jung
发明人： Kwang-Jin Moon , Pil-Kyu Kang , Dae-Lok Bae , Gil-Heyun Choi , Byung-Lyul Park , Dong-Chan Lim , Deok-Young Jung
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/528 , H01L2224/16146 , H01L2225/06541 , H01L2924/01327 , H01L2924/00
摘要： A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure.
摘要翻译：半导体器件包括通孔结构和导电结构。通孔结构具有平坦部分和突出部分的表面。导电结构形成在平面部分的至少一部分上，而不是在通孔结构的突出部分的至少一部分之上。例如，导电结构仅形成在平面部分上，而不形成在任何突出部分上，用于在导电结构和通孔结构之间形成高质量的连接。

5. 发明申请

US20120282736A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE INCLUDING THE SAME 有权
标题翻译：制造半导体器件的方法和制造包括其的半导体封装的方法
公开(公告)号：US20120282736A1
公开(公告)日：2012-11-08
申请号：US13459468
申请日：2012-04-30
申请人： Kwang-Jin MOON , Byung-Lyul PARK , Do-Sun LEE , Gil-Heyun CHOI , Suk-Chul BANG , Dong-Chan LIM , Deok-Young JUNG
发明人： Kwang-Jin MOON , Byung-Lyul PARK , Do-Sun LEE , Gil-Heyun CHOI , Suk-Chul BANG , Dong-Chan LIM , Deok-Young JUNG
IPC分类号： H01L21/50 , H01L21/768
CPC分类号： H01L21/2885 , H01L21/76898 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/15311
摘要： In a method of manufacturing a semiconductor device, a front end of line (FEOL) process may be performed on a semiconductor substrate to form a semiconductor structure. A back end of line (BEOL) process may be performed on the semiconductor substrate to form a wiring structure electrically connected to the semiconductor structure, thereby formed a semiconductor chip. A hole may be formed through a part of the semiconductor chip. A preliminary plug may have a dimple in the hole. The preliminary plug may be expanded into the dimple by a thermal treatment process to form a plug. Thus, the plug may not have a protrusion protruding from the upper surface of the semiconductor chip, so that the plug may be formed by the single CMP process.
摘要翻译：在制造半导体器件的方法中，可以在半导体衬底上执行前端（FEOL）工艺以形成半导体结构。可以在半导体基板上进行后端（BEOL）处理，以形成与半导体结构电连接的布线结构，从而形成半导体芯片。可以通过半导体芯片的一部分形成孔。初步插头可能在孔中有一个凹坑。预先塞子可以通过热处理过程扩展到凹坑中以形成塞子。因此，插头可以不具有从半导体芯片的上表面突出的突起，从而可以通过单个CMP工艺形成插头。

6. 发明授权

US07867841B2 Methods of forming semiconductor devices with extended active regions 有权
标题翻译：形成具有扩展活性区域的半导体器件的方法
公开(公告)号：US07867841B2
公开(公告)日：2011-01-11
申请号：US11968242
申请日：2008-01-02
申请人： Dong-Chan Lim , Byeong-Yun Nam , Soo-Ik Jang , In-Soo Jung
发明人： Dong-Chan Lim , Byeong-Yun Nam , Soo-Ik Jang , In-Soo Jung
IPC分类号： H01L21/8238
CPC分类号： H01L21/76283 , H01L21/84 , H01L27/10873 , H01L27/1203
摘要： A method of forming a semiconductor device can include forming a trench in a semiconductor substrate to define an active region. The trench is filled with a first device isolation layer. A portion of the first device isolation layer is etched to recess a top surface of the first device isolation layer below an adjacent top surface of the active region of the semiconductor substrate and to partially expose a sidewall of the active region. The exposed sidewall of the active region is epitaxially grown to form an extension portion of the active region that extends partially across the top surface of the first device isolation layer in the trench. A second device isolation layer is formed on the recessed first device isolation layer in the trench. The second device isolation layer is etched to expose a top surface of the extension portion of the active region and leave a portion of the second device isolation layer between extension portions of active regions on opposite sides of the trench. An interlayer dielectric is formed on the semiconductor substrate and the second device isolation layer. A conductive contact is formed extending through the interlayer dielectric layer and directly contacting at least a portion of both the active region and the extension portion of the active region overlying the second device isolation layer.
摘要翻译：形成半导体器件的方法可以包括在半导体衬底中形成沟槽以限定有源区。沟槽填充有第一器件隔离层。第一器件隔离层的一部分被蚀刻以将第一器件隔离层的顶表面凹陷在半导体衬底的有源区的相邻顶表面下方并且部分地暴露有源区的侧壁。有源区的暴露的侧壁被外延生长以形成有源区的延伸部分，部分地延伸穿过沟槽中的第一器件隔离层的顶表面。第二器件隔离层形成在沟槽中凹陷的第一器件隔离层上。蚀刻第二器件隔离层以暴露有源区的延伸部分的顶表面，并且将第二器件隔离层的一部分留在沟槽的相对侧上的有源区的延伸部分之间。在半导体衬底和第二器件隔离层上形成层间电介质。形成延伸穿过层间介电层并且直接接触覆盖在第二器件隔离层上的有源区域和有源区域的延伸部分的至少一部分的导电接触。

7. 发明申请

US20100250675A1 SYSTEM AND METHOD FOR TRANSMITTING PERSONAL NETWORKING-BASED BLOG POST, AND SERVER APPLIED TO THE SAME 有权
标题翻译：用于发送基于个人网络的博客POST的系统和方法以及应用于其的服务器
公开(公告)号：US20100250675A1
公开(公告)日：2010-09-30
申请号：US12676620
申请日：2008-10-17
申请人： Chang-Su Lee , Dong-Chan Lim , Su-Kyung Kim , Sung Kim , Sil-Keun Hwang
发明人： Chang-Su Lee , Dong-Chan Lim , Su-Kyung Kim , Sung Kim , Sil-Keun Hwang
IPC分类号： G06F15/16
CPC分类号： G06Q30/02 , G06Q10/10 , H04L51/32
摘要： Disclosed are a system and method for distributing a blog post based on personal networking, and a server to be applied thereto. The system includes a writer terminal unit, which makes a series of settings for forming a blog post containing contents posted by a writer through the writer's blog registered with an online community service, and then distributes the blog post to at least one or more acquaintances blogs registered to personal networking with the writer, sharer/distributor terminal units, which make setting for posting the blog post on the acquaintances blogs, or distributing the blog post to at least one or more other acquaintances blogs registered to personal networking with sharers/distributors, and a service management server, which differentially provides management authority for the blog post to each of the writer and the sharers/distributors, and integrally manages the blog post distributed to a plurality of blogs, based on a path along which the blog post is distributed. The system and method distributes a blog post containing a writer's specific purpose of posting, such as a help-wanted notice, step by step through blogs registered with an online community service, based on trust relationships, thereby providing a notice platform, which is so efficient that an advertiser who writes a blog post, such as a help-wanted notice, can quickly find a qualified person, based on his/her trust relationships.
摘要翻译：公开了一种用于基于个人网络分发博客文章的系统和方法以及要应用于其的服务器。该系统包括作者终端单元，其用于形成博客文章的一系列设置，其中包含由作者通过在线社区服务注册的作者的博客发布的内容，然后将博客文章分发到至少一个或多个熟人博客注册到与作者，分销商/分销商终端单元的个人网络，这些终端单元在熟人博客上发布博客文章的设置，或者将博客文章分发到至少一个或多个其他熟人登记到与共享者/分发者的个人网络的博客，以及服务管理服务器，其基于分发给博客文章的路径，分散到多个博客的博客文章，分别向每个作者和共享者/分发者提供博客文章的管理权限，并且整合管理博客帖子。系统和方法基于信任关系分发包含作者特定发布目的的博客文章，如帮助通知，逐步通过在线社区服务注册的博客，从而提供通知平台撰写博客文章的广告客户（例如帮助通知）可以根据他/她的信任关系快速找到合格的人员。

8. 发明申请

US20090256177A1 Semiconductor device including an ohmic layer 有权
标题翻译：包括欧姆层的半导体器件
公开(公告)号：US20090256177A1
公开(公告)日：2009-10-15
申请号：US12453198
申请日：2009-05-01
申请人： Hee-Sook PARK , Gil-Heyun CHOI , Chang-Won LEE , Byung-Hak LEE , Sun-Pil YOUN , Dong-Chan LIM , Jae-Hwa PARK , Jang-Hee LEE , Woong-Hee SOHN
发明人： Hee-Sook PARK , Gil-Heyun CHOI , Chang-Won LEE , Byung-Hak LEE , Sun-Pil YOUN , Dong-Chan LIM , Jae-Hwa PARK , Jang-Hee LEE , Woong-Hee SOHN
IPC分类号： H01L29/80 , H01L23/498 , H01L23/52
CPC分类号： H01L29/4933 , C23C16/42 , H01L21/28061 , H01L21/28194 , H01L21/28556 , H01L21/76846 , H01L29/517
摘要： In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.
摘要翻译：在欧姆层和形成欧姆层的方法中，包括欧姆层的栅极结构和具有欧姆层的金属布线，欧姆层使用包含钨和硅的钨硅化物形成，原子比在约 1:5至约1:15。可以在室内使用包含钨源气体和硅源气体的反应气体，在约1.0:25.0至约1.0:16.0.0的范围内的分压比获得硅化钨。反应气体可以具有在室的总内部压力的约2.05％至约30.0％的范围内的分压。当欧姆层用于诸如栅极结构或金属布线的导电结构时，导电结构可以具有降低的电阻。

9. 发明授权

US07534709B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07534709B2
公开(公告)日：2009-05-19
申请号：US11233580
申请日：2005-09-23
申请人： Jae-Hwa Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Woong-Hee Sohn , Jong-Ryeol Yoo , Sun-Pil Yun , Jang-Hee Lee , Dong-Chan Lim
发明人： Jae-Hwa Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Woong-Hee Sohn , Jong-Ryeol Yoo , Sun-Pil Yun , Jang-Hee Lee , Dong-Chan Lim
IPC分类号： H01L21/3205
CPC分类号： H01L21/76841 , H01L21/28061 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L29/4933 , H01L29/4941
摘要： Embodiments of the present invention include semiconductor devices that can be made with relatively low resistance, and methods of forming the semiconductor devices. A resistance reducing layer is formed between a polysilicon layer and a metal layer. As a result, an interface resistance between the polysilicon layer and the metal layer is greatly reduced and a distribution of the interface resistance is very uniform. As a result, a conductive structure including the resistance reducing layer has a greatly reduced sheet resistance to improve electrical characteristics of a semiconductor device having the conductive structure.
摘要翻译：本发明的实施例包括可以制造成具有较低电阻的半导体器件，以及形成半导体器件的方法。在多晶硅层和金属层之间形成电阻降低层。结果，多晶硅层和金属层之间的界面电阻大大降低，并且界面电阻的分布非常均匀。结果，包括电阻降低层的导电结构具有大大降低的薄层电阻以改善具有导电结构的半导体器件的电特性。

10. 发明申请

US20060068535A1 Methods of fabricating semiconductor devices 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20060068535A1
公开(公告)日：2006-03-30
申请号：US11216662
申请日：2005-08-31
申请人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Dong-Chan Lim , Byung-Hak Lee , Hee-Sook Park
发明人： Sun-Pil Youn , Chang-Won Lee , Woong-Hee Sohn , Gil-Heyun Choi , Jong-Ryeol Yoo , Dong-Chan Lim , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462 , H01L21/823481
摘要： Methods of forming semiconductor devices are provided. A preliminary gate structure is formed on a semiconductor substrate. The preliminary gate structure includes a gate insulation layer pattern, a polysilicon layer pattern and a conductive layer pattern. A first oxidation process is performed on the preliminary gate structure using an oxygen radical. The first oxidation process is carried out at a first temperature. A second oxidation process is carried out on the oxidized preliminary gate structure to provide a gate structure on the substrate, the second oxidation process being carried out at a second temperature, the second temperature being higher than the first temperature.
摘要翻译：提供了形成半导体器件的方法。在半导体衬底上形成初步栅极结构。预栅极结构包括栅极绝缘层图案，多晶硅层图案和导电层图案。使用氧自由基对预选栅极结构进行第一氧化处理。第一氧化过程在第一温度下进行。在氧化的预选栅极结构上进行第二氧化工艺以在衬底上提供栅极结构，第二氧化工艺在第二温度下进行，第二温度高于第一温度。

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