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1. 发明申请

US20120297097A1 UNIFIED DMA 有权
标题翻译：统一DMA
公开(公告)号：US20120297097A1
公开(公告)日：2012-11-22
申请号：US13566485
申请日：2012-08-03
申请人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
发明人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.
摘要翻译：在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。第一接口电路被配置为根据协议在接口上进行通信。主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输。

2. 发明申请

US20120036289A1 Data Flow Control Within and Between DMA Channels 有权
公开(公告)号：US20120036289A1
公开(公告)日：2012-02-09
申请号：US13276537
申请日：2011-10-19
申请人： Dominic Go , Mark D. Hayter , Puneet Kumar
发明人： Dominic Go , Mark D. Hayter , Puneet Kumar
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.

3. 发明申请

US20100011136A1 Functional DMA 有权
标题翻译：功能DMA
公开(公告)号：US20100011136A1
公开(公告)日：2010-01-14
申请号：US12564610
申请日：2009-09-22
申请人： Dominic Go , Mark D. HAYTER , Zongjian Chen , Weichun Ku
发明人： Dominic Go , Mark D. HAYTER , Zongjian Chen , Weichun Ku
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.
摘要翻译：在一个实施例中，直接存储器访问（DMA）控制器包括发射控制电路，卸载引擎和接收控制电路。发送控制电路被配置为从主机中的地址空间读取第一DMA数据。耦合以从发送控制电路接收第一DMA数据，卸载引擎被配置为对第一DMA数据执行至少第一操作以产生结果。卸载引擎被配置为在向卸载引擎提供第一DMA数据的DMA传送期间至少开始执行第一操作。耦合到卸载引擎以接收结果，接收控制电路被配置为根据描述DMA传输的DMA描述符数据结构将结果写入主机中的地址空间。

4. 发明申请

US20080222317A1 Data Flow Control Within and Between DMA Channels 有权
标题翻译： DMA通道内和之间的数据流控制
公开(公告)号：US20080222317A1
公开(公告)日：2008-09-11
申请号：US11682051
申请日：2007-03-05
申请人： Dominic Go , Mark D. Hayter , Puneet Kumar
发明人： Dominic Go , Mark D. Hayter , Puneet Kumar
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.
摘要翻译：在一个实施例中，直接存储器访问（DMA）控制器包括耦合到发射电路的发射电路和数据流控制电路。发送电路被配置为执行DMA传输，每个DMA传输由存储在存储器中的数据结构中的DMA描述符描述。每个正在使用的DMA通道都有数据结构。数据流控制电路被配置为响应于对应数据结构中的DMA描述符中的数据流控制数据来控制发送电路对每个DMA通道的DMA描述符的处理。

5. 发明申请

US20070073915A1 Functional DMA 有权
公开(公告)号：US20070073915A1
公开(公告)日：2007-03-29
申请号：US11238850
申请日：2005-09-29
申请人： Dominic Go , Mark Hayter , Zongjian Chen , Weichun Ku
发明人： Dominic Go , Mark Hayter , Zongjian Chen , Weichun Ku
IPC分类号： G06F3/00
CPC分类号： G06F13/28
摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.

6. 发明授权

US08713370B2 Non-intrusive processor tracing 有权
标题翻译：非侵入式处理器跟踪
公开(公告)号：US08713370B2
公开(公告)日：2014-04-29
申请号：US13207944
申请日：2011-08-11
申请人： Timothy J. Millet , Shun Wai (“Dominic”) Go , Conrad H. Ziesler
发明人： Timothy J. Millet , Shun Wai (“Dominic”) Go , Conrad H. Ziesler
IPC分类号： G06F11/00
CPC分类号： G06F11/3471 , G06F11/348 , G06F11/3636 , G06F11/3648 , G06F2201/81 , G06F2201/865 , G06F2201/88
摘要： A system, apparatus, and method for writing trace data to storage. Trace data is captured from one or more processors, and then the trace data is written to a trace buffer. The trace data includes program counters of instructions executed by the processors and other debug data. A direct memory access (DMA) controller in a non-real-time block of the system reads trace data from the trace buffer and then writes the trace data to memory via a non-real-time port of a memory controller.
摘要翻译：用于将跟踪数据写入存储器的系统，装置和方法。从一个或多个处理器捕获跟踪数据，然后将跟踪数据写入跟踪缓冲区。跟踪数据包括由处理器执行的指令的程序计数器和其他调试数据。系统非实时块中的直接存储器访问（DMA）控制器从跟踪缓冲器中读取跟踪数据，然后通过存储器控制器的非实时端口将跟踪数据写入存储器。

7. 发明授权

US08495257B2 Network direct memory access 有权
标题翻译：网络直接内存访问
公开(公告)号：US08495257B2
公开(公告)日：2013-07-23
申请号：US12908741
申请日：2010-10-20
申请人： Shailendra S. Desai , Mark D. Hayter , Dominic Go
发明人： Shailendra S. Desai , Mark D. Hayter , Dominic Go
IPC分类号： G06F13/28 , G06F15/167
CPC分类号： H04L49/35 , H04L49/109 , H04L49/352 , H04L69/324
摘要： In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.
摘要翻译：在一个实施例中，系统包括耦合到网络的至少第一节点和第二节点。第二节点包括本地存储器和耦合到本地存储器的直接存储器访问（DMA）控制器。第一节点被配置为将至少第一分组发送到第二节点以访问本地存储器中的数据和至少一个未被编码以访问本地存储器的其他分组。第二节点被配置为从协议栈的数据链路层捕获分组，并且其中DMA控制器被配置为响应于接收到的第一分组而与本地存储器执行多一次传输以访问由第一分组指定的数据从数据链路层。第二个节点被配置为将另一个分组处理到协议栈的顶部。

8. 发明授权

US08443118B2 Data flow control within and between DMA channels 有权
标题翻译： DMA通道内和之间的数据流控制
公开(公告)号：US08443118B2
公开(公告)日：2013-05-14
申请号：US13563127
申请日：2012-07-31
申请人： Dominic Go , Mark D. Hayter , Puneet Kumar
发明人： Dominic Go , Mark D. Hayter , Puneet Kumar
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.
摘要翻译：在一个实施例中，直接存储器访问（DMA）控制器包括耦合到发射电路的发射电路和数据流控制电路。发送电路被配置为执行DMA传输，每个DMA传输由存储在存储器中的数据结构中的DMA描述符描述。每个正在使用的DMA通道都有一个数据结构。数据流控制电路被配置为响应于对应数据结构中的DMA描述符中的数据流控制数据来控制发送电路对每个DMA通道的DMA描述符的处理。

9. 发明授权

US08209446B2 DMA controller that passes destination pointers from transmit logic through a loopback buffer to receive logic to write data to memory 有权
标题翻译： DMA控制器通过环回缓冲区传送来自传输逻辑的目标指针，以接收将数据写入存储器的逻辑
公开(公告)号：US08209446B2
公开(公告)日：2012-06-26
申请号：US13221622
申请日：2011-08-30
申请人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
发明人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.
摘要翻译：在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。第一接口电路被配置为根据协议在接口上进行通信。主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输。

10. 发明申请

US20110314186A1 Unified DMA 有权
标题翻译：统一DMA
公开(公告)号：US20110314186A1
公开(公告)日：2011-12-22
申请号：US13221622
申请日：2011-08-30
申请人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
发明人： Dominic Go , Mark D. Hayter , Zongjian Chen , Ruchi Wadhawan
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.
摘要翻译：在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。第一接口电路被配置为根据协议在接口上进行通信。主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输。

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