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1. 发明申请

US20080317106A1 MCU WITH INTEGRATED VOLTAGE ISOLATOR AND INTEGRATED GALVANICALLY ISOLATED ASYNCHRONOUS SERIAL DATA LINK 失效
标题翻译：具有集成电压隔离器的MCU和集成的气象分离异步串行数据链路
公开(公告)号：US20080317106A1
公开(公告)日：2008-12-25
申请号：US12165011
申请日：2008-06-30
申请人： Ka Y. Leung , Donald E. Alfano , David Bresemann
发明人： Ka Y. Leung , Donald E. Alfano , David Bresemann
IPC分类号： H04B1/40
CPC分类号： G06F13/4072 , G06F13/4278 , H01L2224/05554 , H01L2224/48137 , H01L2224/48247 , H01L2224/49171 , H01L2224/49175 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： An integrated circuit comprises a first microcontroller unit for executing instructions in accordance with a first clock frequency. The microcontroller located on a first die and includes a first processing core for providing a parallel stream of data in accordance with the first clock frequency. A second microcontroller unit executes instructions in accordance with the first clock frequency. The second microcontroller is located on a second die and includes a second processing core for receiving the parallel stream of data in accordance with the first clock frequency. Capacitive isolation circuitry connected with the first microcontroller unit and the second microcontroller unit provides a high voltage isolation link between the first and the second microcontroller units. The capacitive isolation circuitry distributing a first portion of a high voltage isolation signal across a first group of capacitors associated with the first microcontroller unit and distributes a second portion of the high voltage isolation signal across a second group of capacitors associated with the second microcontroller unit. The capacitive isolation circuitry further transmits data from the parallel data stream between the first microcontroller and the second microcontroller in a serial data stream in accordance with the second clock frequency.
摘要翻译：集成电路包括用于根据第一时钟频率执行指令的第一微控制器单元。微控制器位于第一管芯上并且包括用于根据第一时钟频率提供并行数据流的第一处理核心。第二微控制器单元根据第一时钟频率执行指令。第二微控制器位于第二管芯上，并且包括用于根据第一时钟频率接收并行数据流的第二处理核。与第一微控制器单元和第二微控制器单元连接的电容隔离电路在第一和第二微控制器单元之间提供高电压隔离链路。电容隔离电路将高电压隔离信号的第一部分跨越与第一微控制器单元相关联的第一组电容器分配，并将第二部分高电压隔离信号分配到与第二微控制器单元相关联的第二组电容器上。电容隔离电路还根据第二时钟频率在串行数据流中从第一微控制器和第二微控制器之间的并行数据流传输数据。

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