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1. 发明授权

US08839054B2 Read only memory (ROM) with redundancy 有权
标题翻译：只读存储器（ROM）冗余
公开(公告)号：US08839054B2
公开(公告)日：2014-09-16
申请号：US13445187
申请日：2012-04-12
申请人： George M. Braceras , Albert M. Chu , Kevin W. Gorman , Michael R. Ouellette , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
发明人： George M. Braceras , Albert M. Chu , Kevin W. Gorman , Michael R. Ouellette , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G06F11/0793 , G11C17/00 , G11C29/4401 , G11C29/822
摘要： A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.
摘要翻译：提供了具有冗余性和使用方法的只读存储器（ROM）。具有冗余的ROM包括耦合到具有一个或多个冗余修复的修复电路的可编程阵列。一个或多个冗余修复包括字地址匹配逻辑块，数据I / O地址和三态缓冲器。字地址匹配逻辑块作为控制输入提供给三态缓冲器，并且将数据I / O地址作为输入提供给三态缓冲器。提供每个冗余修复的三态缓冲器的输出作为一个或多个逻辑器件的第一输入。提供ROM位单元阵列的一个或多个数据输出作为一个或多个逻辑器件中的相应一个的第二输入。

2. 发明申请

US20130211749A1 EMBEDDED PHOTON EMISSION CALIBRATION (EPEC) 有权
标题翻译：嵌入式光电子发射校准（EPEC）
公开(公告)号：US20130211749A1
公开(公告)日：2013-08-15
申请号：US13396775
申请日：2012-02-15
申请人： Albert M. Chu , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
发明人： Albert M. Chu , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
IPC分类号： G01R31/308 , G06F19/00
CPC分类号： G01R31/311
摘要： A semiconductor device structure is embedded within a semiconductor chip that calibrates a photon-emission luminosity scale by running multiple known currents through the device. The method comprises embedding at least one photon emission device in an integrated circuit having at least one functional device. A control current is applied to the at least one photon emission device. The photon emission intensity produced by the at least one photon emission device is captured. The current density of the at least one photon emission device is calculated. A test current is applied to the at least one functional device. The photon emission intensity produced by the at least one functional device is captured. The current density of the at least one functional device is estimated based on a comparison with the calculated current density of the at least one photon emission device.
摘要翻译：半导体器件结构嵌入半导体芯片内，通过运行多个已知电流通过器件来校准光子发射光度标度。该方法包括将至少一个光子发射装置嵌入到具有至少一个功能装置的集成电路中。控制电流被施加到至少一个光子发射装置。捕获由至少一个光子发射装置产生的光子发射强度。计算出至少一个光子发射装置的电流密度。测试电流被施加到所述至少一个功能装置。捕获由至少一个功能装置产生的光子发射强度。基于与计算出的至少一个光子发射装置的电流密度的比较来估计至少一个功能装置的电流密度。

3. 发明授权

US07573300B2 Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same 有权
标题翻译：集成电路中动态逻辑门控电路的电流控制机制及其调节方法
公开(公告)号：US07573300B2
公开(公告)日：2009-08-11
申请号：US11623112
申请日：2007-01-15
申请人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
摘要翻译：一种集成电路，其包括栅极控制电压发生器，其将电流控制栅极电压提供给各自具有保持电路的相应多个动态逻辑电路的多个电流控制装置。栅极控制电压发生器通过电流控制栅极电压提供流过保持器电路的保持器电流量的全局控制，以便增强动态逻辑电路的性能。

4. 发明申请

US20090179670A1 PERFORMANCE INVERSION DETECTION CIRCUIT AND A DESIGN STRUCTURE FOR THE SAME 审中-公开
标题翻译：性能反相检测电路及其设计结构
公开(公告)号：US20090179670A1
公开(公告)日：2009-07-16
申请号：US12014430
申请日：2008-01-15
申请人： Albert M. Chu , John A. Fifield , Daryl M. Seitzer , Hongfei Wu
发明人： Albert M. Chu , John A. Fifield , Daryl M. Seitzer , Hongfei Wu
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F2200/447 , H03F2203/45586 , H03F2203/45618 , H03F2203/45622
摘要： A circuit containing a parallel connection of a first sub-circuit and a second sub-circuit is provided. The first sub-circuit comprises a serial connection of a first field effect transistor having a first threshold voltage and a first voltage dividing device. The second sub-circuit comprises a serial connection of a second field effect transistor having a second threshold voltage, which is different from the first threshold voltage, and a second voltage dividing device. The voltage between the first field effect transistor and the first voltage dividing device is compared with the voltage between the second field effect transistor and the second voltage dividing device so that a signal may be generated at a temperature at which the ratio of a performance parameter such as on-current between the first and second field effect transistors crosses over a predefined value. The signal may be advantageously employed to actively control circuit characteristics.
摘要翻译：提供了包含第一子电路和第二子电路的并联连接的电路。第一子电路包括具有第一阈值电压的第一场效应晶体管和第一分压装置的串联连接。第二子电路包括具有与第一阈值电压不同的第二阈值电压的第二场效应晶体管的串联连接和第二分压装置。将第一场效应晶体管和第一分压装置之间的电压与第二场效应晶体管和第二分压装置之间的电压进行比较，使得可以在这样的温度下产生信号，因为第一和第二场效应晶体管之间的导通电流跨越预定值。可以有利地使用该信号来主动地控制电路特性。

5. 发明授权

US07471114B2 Design structure for a current control mechanism for power networks and dynamic logic keeper circuits 失效
标题翻译：用于电力网络和动态逻辑门控电路的电流控制机构的设计结构
公开(公告)号：US07471114B2
公开(公告)日：2008-12-30
申请号：US11851133
申请日：2007-09-06
申请人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A design structure for an integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
摘要翻译：一种用于集成电路的设计结构，其包括栅极控制电压发生器，其将电流控制栅极电压提供给各自具有保持电路的相应多个动态逻辑电路的多个电流控制装置。栅极控制电压发生器通过电流控制栅极电压提供流过保持器电路的保持器电流量的全局控制，以便增强动态逻辑电路的性能。

6. 发明授权

US07141998B1 Method and apparatus for burn-in optimization 失效
公开(公告)号：US07141998B1
公开(公告)日：2006-11-28
申请号：US10908620
申请日：2005-05-19
申请人： Wagdi W. Abadeer , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , Harold Pilo , Daryl M. Seitzer
IPC分类号： G01R31/02
CPC分类号： G01R31/287 , G01R31/2874
摘要： The present invention provides a method and apparatus for optimizing the burn-in of integrated circuits. One embodiment of the method comprises: performing a first portion of the burn-in process of the integrated circuit; monitoring a power dissipation of the integrated circuit during the first portion of the burn-in process; increasing a burn-in temperature until the power dissipation of the integrated circuit reaches a predetermined maximum power dissipation; and performing a subsequent portion of the burn-in process of the integrated circuit at the increased burn-in temperature.

7. 发明授权

US06487101B1 Use of search lines as global bitlines in a cam design 有权
标题翻译：在凸轮设计中使用搜索线作为全局位线
公开(公告)号：US06487101B1
公开(公告)日：2002-11-26
申请号：US09968814
申请日：2001-10-02
申请人： Jonathan B. Ashbrook , Robert E. Busch , Albert M. Chu , Daryl M. Seitzer
发明人： Jonathan B. Ashbrook , Robert E. Busch , Albert M. Chu , Daryl M. Seitzer
IPC分类号： G11C1500
CPC分类号： G11C15/04 , G11C15/043
摘要： A method and structure for a content addressable memory (CAM) array having a plurality of memory cells. Each of the memory cells has capacitive storage devices, transistors connected to the storage devices, a wordline connected to and controlling the transistors, bitlines connected to the storage devices through the transistors, combined search and global bitlines connected to the capacitive storage devices. These cells are further arranged into columns, each containing multiplexers connected to the combined search and global bitlines, data-in lines connected to the multiplexers, and search-data lines connected to the multiplexers. Further, the multiplexers select between the data-in lines and the search-data lines to allow the combined search and global bitlines to be alternatively used as data lines and search lines. Also, in the invention each of the columns further has drivers between the multiplexers and the combined search and global bitlines. The drivers drive signals between the multiplexers and the combined search and global bitlines during search and write operations.
摘要翻译：一种具有多个存储单元的内容可寻址存储器（CAM）阵列的方法和结构。每个存储单元具有电容存储器件，连接到存储器件的晶体管，连接到晶体管和控制晶体管的字线，通过晶体管连接到存储器件的位线，连接到电容存储器件的组合搜索和全局位线。这些单元进一步排列成列，每列包含连接到组合搜索和全局位线的多路复用器，连接到多路复用器的数据输入线以及连接到多路复用器的搜索数据线。此外，多路复用器在数据输入行和搜索数据行之间进行选择以允许将组合搜索和全局位线替代地用作数据线和搜索行。此外，在本发明中，每个列还具有多路复用器和组合的搜索和全局位线之间的驱动器。在搜索和写入操作期间，驱动器在多路复用器之间驱动信号和组合的搜索和全局位线。

8. 发明授权

US08519772B2 Alternate power gating enablement 失效
标题翻译：备用电源门控启用
公开(公告)号：US08519772B2
公开(公告)日：2013-08-27
申请号：US13075652
申请日：2011-03-30
申请人： Albert M. Chu , Daryl M. Seitzer , Rohit Shetty , Douglas W. Stout
发明人： Albert M. Chu , Daryl M. Seitzer , Rohit Shetty , Douglas W. Stout
IPC分类号： H03K17/687
CPC分类号： H03K19/0016
摘要： Structures and methods for implementing alternating power gating in integrated circuits. A semiconductor structure includes a power gated circuit including a group of power gate switches and an alternating enable generator that generates enabling signals. Each respective one of the power gate switches is enabled by a respective one of the enabling signals. The alternating generator generates the enabling signals such that a first enabled power gate switch is alternated amongst the group of power gate switches.
摘要翻译：在集成电路中实现交流电源门控的结构和方法。半导体结构包括电源门控电路，其包括一组电源门开关和产生使能信号的交替使能发生器。每个相应的一个功率门开关由使能信号中的相应一个使能。交替发电机产生使能信号，使得第一使能电源门极开关在一组电源门开关之间交替。

9. 发明申请

US20090240875A1 CONTENT ADDRESSABLE MEMORY WITH HIDDEN TABLE UPDATE, DESIGN STRUCTURE AND METHOD 审中-公开
标题翻译：内容可寻址存储器，具有隐藏表更新，设计结构和方法
公开(公告)号：US20090240875A1
公开(公告)日：2009-09-24
申请号：US12050340
申请日：2008-03-18
申请人： Albert M. Chu , Paul C. Parries , Daryl M. Seitzer
发明人： Albert M. Chu , Paul C. Parries , Daryl M. Seitzer
IPC分类号： G11C15/04 , G11C7/00
CPC分类号： G11C15/043 , G11C11/406
摘要： Disclosed are embodiments of memory circuit having two discrete memory devices with two discrete memory arrays that store essentially identical data banks. The first device is a conventional memory adapted to perform all maintenance operations that require read functions (i.e., all update and refresh operations). The second device is a DRAM-based CAM device adapted to perform parallel search and overwrite operations only. Performance of overwrite operations by the second device occurs in conjunction with performance of maintenance operations by the first device so that corresponding memory cells in the two devices store essentially identical data values. Since the data banks in the memory devices are essentially identical and since maintenance and parallel search operations are not performed by the same device, the parallel search operations can be performed without interruption. Also disclosed are embodiments of an associated design structure and method.
摘要翻译：公开了具有两个分立存储器件的存储器电路的实施例，其具有存储基本上相同的数据库的两个分立存储器阵列。第一设备是适于执行需要读取功能（即，所有更新和刷新操作）的所有维护操作的常规存储器。第二设备是仅适用于执行并行搜索和重写操作的基于DRAM的CAM设备。第二设备的覆盖操作的性能与第一设备的维护操作的性能一起发生，使得两个设备中的相应存储器单元存储基本上相同的数据值。由于存储器件中的数据库基本上相同，并且由于维护和并行搜索操作不由同一设备执行，所以可以不中断地执行并行搜索操作。还公开了相关设计结构和方法的实施例。

10. 发明授权

US07548080B2 Method and apparatus for burn-in optimization 失效
标题翻译：老化优化的方法和装置
公开(公告)号：US07548080B2
公开(公告)日：2009-06-16
申请号：US11538833
申请日：2006-10-05
申请人： Wagdi W. Abadeer , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , Harold Pilo , Daryl M. Seitzer
IPC分类号： G01R31/02
CPC分类号： G01R31/287 , G01R31/2874
摘要： The present invention provides a method and apparatus for optimizing the burn-in of integrated circuits. One embodiment of the method comprises: performing a first portion of the burn-in process of the integrated circuit; monitoring a power dissipation of the integrated circuit during the first portion of the burn-in process; increasing a burn-in temperature until the power dissipation of the integrated circuit reaches a predetermined maximum power dissipation; and performing a subsequent portion of the burn-in process of the integrated circuit at the increased burn-in temperature.
摘要翻译：本发明提供一种用于优化集成电路的老化的方法和装置。该方法的一个实施例包括：执行集成电路的老化过程的第一部分; 在老化过程的第一部分期间监测集成电路的功耗; 增加老化温度，直到集成电路的功耗达到预定的最大功耗; 以及在增加的老化温度下执行集成电路的老化过程的后续部分。

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