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1. 发明授权

US06560698B1 Register change summary resource 有权
标题翻译：注册更改摘要资源
公开(公告)号：US06560698B1
公开(公告)日：2003-05-06
申请号：US09306879
申请日：1999-05-07
申请人： Daniel P. Mann
发明人： Daniel P. Mann
IPC分类号： G06F944
CPC分类号： G06F9/5011 , G06F9/30101 , G06F2209/507
摘要： A microcontroller provides a register change summary resource for summarizing register changes. Selected system registers within each resource are coupled to bits in resource change registers of the register change summary resource using logic that tracks accesses to the system registers. Each resource change register is coupled to a bit in a summary register. For systems with numerous system registers, each summary register may be coupled to a bit in a higher-level summary register. The register change summary resource further provides a software-controlled bit mask register. A change in a summary or resource change register may trigger a processor interrupt. Each register in the register change summary resource can be reset, also under software control. The registers within the register change summary resource are accessible through a dedicated software development port.
摘要翻译：微控制器提供用于总结寄存器变化的寄存器改变汇总资源。使用跟踪对系统寄存器的访问的逻辑，将每个资源内的所选系统寄存器耦合到寄存器改变概要资源的资源改变寄存器中的位。每个资源改变寄存器耦合到汇总寄存器中的位。对于具有多个系统寄存器的系统，每个汇总寄存器可以耦合到较高级别的汇总寄存器中的位。寄存器更改汇总资源还提供了软件控制的位掩码寄存器。摘要或资源更改寄存器的更改可能会触发处理器中断。寄存器中的每个寄存器更改摘要资源都可以复位，也可以在软件控制下进行。寄存器更改摘要资源中的寄存器可通过专用软件开发端口访问。

2. 发明授权

US06457078B1 Multi-purpose bi-directional control bus for carrying tokens between initiator devices and target devices 有权
标题翻译：多用途双向控制总线，用于在启动器设备和目标设备之间承载令牌
公开(公告)号：US06457078B1
公开(公告)日：2002-09-24
申请号：US09334884
申请日：1999-06-17
申请人： James R. Magro , Daniel P. Mann
发明人： James R. Magro , Daniel P. Mann
IPC分类号： G06F100
CPC分类号： G06F13/37
摘要： A communication protocol is implemented by a control bus using multi-purpose bi-directional signal lines. The bi-directional signal lines provide a single control path shared among any number of system devices. Tokens, defined by the combination of states of the bi-directional signal lines, are transmitted over the control bus to other system devices. A token can represent a number of control commands. A received token is decoded by a system device using decode logic into an appropriate control command associated with the token according to a predefined logic table. Since a token can represent a control command only originated target devices or a control command only originated by initiator devices, the control bus can support both types of control commands with fewer pincount and point-to-point connections than conventional unidirectional control signalling.
摘要翻译：通信协议由使用多用途双向信号线的控制总线实现。双向信号线提供在任何数量的系统设备之间共享的单个控制路径。通过双向信号线的状态的组合定义的令牌通过控制总线发送到其他系统设备。令牌可以表示多个控制命令。接收的令牌由系统设备使用解码逻辑解码成根据预定逻辑表与令牌相关联的适当的控制命令。由于令牌可以表示控制命令，仅起始目标设备或控制命令仅由启动器设备发起，所以控制总线可以支持具有比常规单向控制信令更少的引脚数和点对点连接的两种类型的控制命令。

3. 发明授权

US06269454B1 Maintaining object information concurrent with data optimization for debugging 有权
标题翻译：维护对象信息与数据优化并发进行调试
公开(公告)号：US06269454B1
公开(公告)日：2001-07-31
申请号：US09187852
申请日：1998-11-06
申请人： Daniel P. Mann , Gary M. Godfrey
发明人： Daniel P. Mann , Gary M. Godfrey
IPC分类号： G06F1100
CPC分类号： G06F11/3636
摘要： A debugging environment maintains object information (e.g., object size) concurrently with data optimization operations by a write buffer of a target system. Within the target system, a system bus is coupled between a system memory and a microcontroller. A data optimization operation by the write buffer is detected by monitoring of a merge signal of the system bus by a bus monitoring device. When a data optimization operation is detected, data optimization attributes (e.g., object information, data and address) associated with the data optimization operation are captured in the form of an object information signal responsive to a capture signal from the bus monitoring device. The data optimization attributes may be stored in either a trace cache of the target system or a memory of external trace capture equipment connected to the debug port, or a memory of the bus monitoring device. In providing the data optimization attributes external to the microcontroller, the data optimization attribute may be temporarily held by trace pins of a debug port of the microcontroller. The data optimization attributes may be extracted from the object information signal and processed by the external trace capture equipment or the bus monitoring device. By processing the data optimization attributes, pre-optimization write object values may be reconstructed.
摘要翻译：调试环境通过目标系统的写缓冲器与数据优化操作同时维护对象信息（例如，对象大小）。在目标系统内，系统总线耦合在系统存储器和微控制器之间。通过由总线监视装置监视系统总线的合并信号来检测写缓冲器的数据优化操作。当检测到数据优化操作时，响应于来自总线监控设备的捕获信号，以对象信息信号的形式捕获与数据优化操作相关联的数据优化属性（例如，对象信息，数据和地址）。数据优化属性可以存储在目标系统的跟踪缓存或连接到调试端口的外部跟踪捕获设备的存储器或总线监视设备的存储器中。在提供微控制器外部的数据优化属性时，数据优化属性可能由微控制器的调试端口的跟踪引脚暂时保持。可以从对象信息信号中提取数据优化属性，并由外部跟踪捕获设备或总线监视设备进行处理。通过处理数据优化属性，可以重构预优化写对象值。

4. 发明授权

US6094729A Debug interface including a compact trace record storage 失效
标题翻译：调试界面包括一个紧凑的跟踪记录存储
公开(公告)号：US6094729A
公开(公告)日：2000-07-25
申请号：US992361
申请日：1997-12-17
申请人： Daniel P. Mann
发明人： Daniel P. Mann
IPC分类号： G06F11/28 , G06F11/26 , G06F11/34 , G06F11/36 , H03K19/003
CPC分类号： G06F11/3636 , G06F11/348 , G06F11/3656 , G06F11/261 , G06F11/3419 , G06F11/3466 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： In-circuit emulation (ICE) and software debug facilities are included in a processor via a debug interface that interfaces a target processor to a host system. The debug interface includes a trace controller that monitors signals produced by the target processor to detect specified conditions and produce a trace record of the specified conditions including a notification of the conditions are selected information relating to the conditions. The trace controller formats a trace information record and stores the trace information record in a trace buffer in a plurality of trace data storage elements. The trace data storage elements have a format that includes a trace code (TCODE) field indicative of a type of trace information and a trace data (TDATA) field indicative of a type of trace information data.
摘要翻译：在线仿真（ICE）和软件调试功能通过调试接口包含在处理器中，该接口将目标处理器与主机系统相连接。调试接口包括跟踪控制器，其监视由目标处理器产生的信号以检测指定的条件并产生指定条件的跟踪记录，包括条件的通知是与条件相关的所选信息。跟踪控制器格式化跟踪信息记录，并将跟踪信息记录存储在多个跟踪数据存储元素中的跟踪缓冲器中。跟踪数据存储元件具有包括指示跟踪信息类型的跟踪代码（TCODE）字段和指示跟踪信息数据类型的跟踪数据（TDATA）字段的格式。

5. 发明授权

US06546482B1 Invalid configuration detection resource 有权
标题翻译：配置检测资源无效
公开(公告)号：US06546482B1
公开(公告)日：2003-04-08
申请号：US09306871
申请日：1999-05-07
申请人： James R. Magro , David F. Tobias , Daniel P. Mann
发明人： James R. Magro , David F. Tobias , Daniel P. Mann
IPC分类号： G06F15177
CPC分类号： G06F11/0772 , G06F11/0721 , G06F11/0751 , G06F11/3648 , G06F11/366
摘要： An invalid configuration detection resource for identifying and reporting conflicts between system resources of a microcontroller or other device is provided. Selected system registers within each resource are monitored by discrete hardware logic within the invalid configuration detection resource. For each resource, a status register provides an encoding of the configuration for that resource. The invalid configuration detection resource then compares the status registers for invalid combinations, and encodes this information in a system status register. Alternatively, the invalid configuration detection resource monitors each selected system register, independent of the resource to which it belongs. Improper combinations of registers are then encoded in a system status register. An alternative embodiment uses software to replace the discrete hardware logic with a table that specifies invalid register combinations. The invalid configuration detection resource further provides a software-controlled bit mask register.
摘要翻译：提供用于识别和报告微控制器或其他设备的系统资源之间的冲突的无效配置检测资源。每个资源内的所选系统寄存器由无效配置检测资源内的离散硬件逻辑进行监控。对于每个资源，状态寄存器提供该资源的配置的编码。无效配置检测资源然后比较无效组合的状态寄存器，并将该信息编码在系统状态寄存器中。或者，无效配置检测资源独立于其所属的资源来监视每个所选择的系统寄存器。寄存器的不正确组合然后被编码在系统状态寄存器中。替代实施例使用软件来用指定无效寄存器组合的表来替换离散硬件逻辑。无效配置检测资源还提供软件控制的位屏蔽寄存器。

6. 发明授权

US5717933A Interrupt handling that disables interrupts upon saving the registers 失效
标题翻译：中断处理在保存寄存器时禁止中断
公开(公告)号：US5717933A
公开(公告)日：1998-02-10
申请号：US705033
申请日：1996-08-29
申请人： Daniel P. Mann
发明人： Daniel P. Mann
IPC分类号： G06F9/48 , G06F9/30 , G06F9/46
CPC分类号： G06F9/30123 , G06F9/30101 , G06F9/462
摘要： To speed up interrupt processing by interrupt handlers executing with interrupts disabled, one or more processor registers in the computer system are reserved for exclusive use by software executing with interrupt disabled. Interrupt processing code can be written in a high level language. If the code generated by the high level language compiler uses non-reserved registers, these registers are saved by the interrupt handler in the reserved registers before the interrupt processing code is invoked. After execution of the interrupt processing code, the interrupt handler restores the non-reserved registers from the reserved registers. Saving the non-reserved registers in the reserved registers rather than in a memory improves the interrupt processing speed.
摘要翻译：为了加快中断处理程序的中断处理速度，禁止执行中断，计算机系统中的一个或多个处理器寄存器被保留供中断禁止执行的软件专用。中断处理代码可以用高级语言编写。如果高级语言编译器生成的代码使用非保留寄存器，则在调用中断处理代码之前，这些寄存器由中断处理程序保存在保留寄存器中。执行中断处理代码后，中断处理程序从保留的寄存器中恢复非保留寄存器。将保留寄存器保存在保留寄存器而不是存储器中，可以提高中断处理速度。

7. 发明授权

US06260081B1 Direct memory access engine for supporting multiple virtual direct memory access channels 有权
标题翻译：直接内存访问引擎，用于支持多个虚拟直接内存访问通道
公开(公告)号：US06260081B1
公开(公告)日：2001-07-10
申请号：US09198797
申请日：1998-11-24
申请人： James R. Magro , Daniel P. Mann , Floyd Goodrich, III
发明人： James R. Magro , Daniel P. Mann , Floyd Goodrich, III
IPC分类号： G06F300
CPC分类号： G06F13/28
摘要： A direct memory access engine supports multiple virtual direct memory access channels. The direct memory access engine includes a direct memory access controller and a parameter table in memory containing parameters for a plurality of virtual direct memory access channels. The controller engine provides a single physical direct memory access channel and a plurality of virtual direct memory access channels. One direct memory access channel of the plurality of virtual direct memory access channels may be active at a given time. The parameters for the active channel may be loaded from the parameter table to a physical direct memory access control block and a physical direct memory access channel resource of the direct memory access controller. The physical direct memory access control block of the direct memory access controller utilizes the physical direct memory access channel resource to perform a direct memory access transfer for the active channel based on the loaded parameters. The physical direct memory access channel resource is shared by the plurality of virtual direct memory access channels. The direct memory access engine further includes a direct memory access request line and a direct memory access acknowledge line for an active channel of the plurality of virtual direct memory access channels.
摘要翻译：直接内存访问引擎支持多个虚拟直接内存访问通道。直接存储器访问引擎包括直接存储器访问控制器和存储器中的参数表，其包含用于多个虚拟直接存储器访问通道的参数。控制器引擎提供单个物理直接存储器访问通道和多个虚拟直接存储器访问通道。多个虚拟直接存储器访问通道中的一个直接存储器访问通道可以在给定时间处于活动状态。活动通道的参数可以从参数表加载到直接存储器访问控制器的物理直接存储器访问控制块和物理直接存储器访问信道资源。直接存储器访问控制器的物理直接存储器访问控制块利用物理直接存储器访问信道资源，以基于所加载的参数为活动信道执行直接存储器访问传输。物理直接存储器访问信道资源由多个虚拟直接存储器访问信道共享。直接存储器访问引擎还包括用于多个虚拟直接存储器访问信道中的活动信道的直接存储器访问请求线和直接存储器访问确认线。

8. 发明授权

US6023561A System for processing traceable cache trace information 失效
标题翻译：用于处理可跟踪缓存跟踪信息的系统
公开(公告)号：US6023561A
公开(公告)日：2000-02-08
申请号：US456884
申请日：1995-06-01
申请人： Daniel P. Mann
发明人： Daniel P. Mann
IPC分类号： G06F11/25 , G06F11/34 , G06F11/36 , G06F11/00
CPC分类号： G06F11/3636 , G06F11/25 , G06F11/3466
摘要： A trace analysis system for tracing the operation of a processor. The trace analysis system includes a process data module and a process instructions module. The process data module processes data accesses of selected test data. The process instruction module processes instruction execution of the selected test data based upon the detection of a non-sequential instruction having a target address. The process instructions module uses the target address of the non-sequential instruction to determine an instruction sequence.
摘要翻译：用于跟踪处理器操作的跟踪分析系统。跟踪分析系统包括过程数据模块和过程指令模块。过程数据模块处理所选测试数据的数据访问。处理指令模块基于检测到具有目标地址的非顺序指令来处理所选择的测试数据的指令执行。处理指令模块使用非顺序指令的目标地址来确定指令序列。

9. 发明授权

US06185732B2 Software debug port for a microprocessor 失效
标题翻译：微处理器的软件调试端口
公开(公告)号：US06185732B2
公开(公告)日：2001-02-06
申请号：US08923597
申请日：1997-08-25
申请人： Daniel P. Mann , Carl K. Wakeland
发明人： Daniel P. Mann , Carl K. Wakeland
IPC分类号： G06F945
CPC分类号： G06F11/3636 , G06F11/348 , G06F11/3656
摘要： A processor-based device incorporating a software debug port that utilizes a JTAG or similar standardized interface, thereby providing a software debug communication mechanism that does not require a special bond-out package. In one embodiment of the invention, only standard JTAG pins are used for communications between a host platform and a target system incorporating a target processor. In another embodiment of the invention, the software debug port of the target processor is augmented for higher-speed access via optional sideband signals. When used in conjunction with an on-chip trace cache, the software debug port provides trace information for reconstructing instruction execution flow on the processor and is also capable of examining register contents without halting processor operation. The software debug port alleviates many of the packaging and clock synchronization problems confronting existing debug solutions.
摘要翻译：一种基于处理器的设备，其结合使用JTAG或类似标准化接口的软件调试端口，从而提供不需要特殊结合包的软件调试通信机制。在本发明的一个实施例中，只有标准JTAG引脚用于主机平台和结合目标处理器的目标系统之间的通信。在本发明的另一个实施例中，目标处理器的软件调试端口通过可选的边带信号被增强以用于更高速度的接入。当与片上跟踪缓存一起使用时，软件调试端口提供跟踪信息，用于在处理器上重建指令执行流程，并且还能够在不停止处理器操作的情况下检查寄存器内容。软件调试端口减轻了现有调试解决方案面临的许多封装和时钟同步问题。

10. 发明授权

US5978902A Debug interface including operating system access of a serial/parallel debug port 失效
标题翻译：调试接口，包括串行/并行调试端口的操作系统访问
公开(公告)号：US5978902A
公开(公告)日：1999-11-02
申请号：US992276
申请日：1997-12-17
申请人： Daniel P. Mann
发明人： Daniel P. Mann
IPC分类号： G06F11/26 , G06F11/34 , G06F11/36 , G06F11/00
CPC分类号： G06F11/3636 , G06F11/348 , G06F11/3632 , G06F11/3656 , G06F11/261 , G06F11/3466 , G06F2201/86 , G06F2201/865 , G06F2201/87 , G06F2201/88
摘要： A debug interface supports data transfer using read and write system calls that communicate data without stopping an executing kernel. The printf( ) command passes an information string to an executing operating system. The information string summons the operating system to use a serial debug port to signal to a debug device, such as a host system, that is connected to the serial port. The debug interface-supported read and write operations and system calls allow the kernel and executing applications software, respectively, to continue executing during the read and write data transfers. The debug interface includes support for a plurality of extended function sideband signals that extend the functionality of the read and write functionality to allow the processor to concurrently run kernel and application programs while transferring data using read and write operation. The extended function sideband signals include a command acknowledge signal (CMDACK), a dual-purpose break execution and trace control signal (BRTC), an execution stopped and receive data signal (STOPTX), and an off-chip trigger event signal (TRIG). The debug interface further includes a buffer for transferred data The kernel may run a first data transfer command which is not fully transmitted when a second data transfer command is issued. The operating system supports buffering of the data evoked by the second data transfer command using a conventional queuing operation.
摘要翻译：调试接口支持使用读和写系统调用进行数据传输，而不会停止执行的内核来传送数据。 printf（）命令将信息字符串传递给执行的操作系统。信息字符串召唤操作系统以使用串行调试端口向连接到串行端口的调试设备（如主机系统）发出信号。调试接口支持的读写操作和系统调用允许内核和执行应用软件分别在读和写数据传输期间继续执行。调试接口包括对多个扩展功能边带信号的支持，其扩展了读写功能的功能，以允许处理器在使用读和写操作传送数据的同时运行内核和应用程序。扩展功能边带信号包括命令确认信号（CMDACK），双用途中断执行和跟踪控制信号（BRTC），执行停止和接收数据信号（STOPTX）以及片外触发事件信号（TRIG）。调试接口还包括用于传送数据的缓冲器。当发出第二数据传输命令时，内核可以运行未完全传输的第一数据传输命令。操作系统支持使用常规排队操作来缓冲由第二数据传输命令引起的数据。

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