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1. 发明授权

US07822038B2 Packet processing system architecture and method 有权
标题翻译：分组处理系统的架构和方法
公开(公告)号：US07822038B2
公开(公告)日：2010-10-26
申请号：US11860045
申请日：2007-09-24
申请人： David K. Parker , Erik R. Swenson , Michael M. Yip , Christopher J. Young
发明人： David K. Parker , Erik R. Swenson , Michael M. Yip , Christopher J. Young
IPC分类号： H04L12/28
CPC分类号： H04L47/2441 , H04L47/10 , H04L47/2433 , H04L47/36 , H04L49/901
摘要： A packet processing system architecture and method are provided. According to a first aspect of the invention, a plurality of quality of service indicators are provided for a packet, each with an assigned priority, and a configurable priority resolution scheme is utilized to select one of the quality of service indicators for assigning to the packet. According to a second aspect of the invention, wide data paths are utilized in selected areas of the system, while avoiding universal utilization of the wide data paths in the system. According to a third aspect of the invention, one or more stacks are utilized to facilitate packet processing. According to a fourth aspect of the invention, a packet size determiner is allocated to a packet from a pool of packet size determiners, and is returned to the pool upon or after determining the size of the packet. According to a fifth aspect of the invention, a packet is buffered upon or after ingress thereof to the system, and a packet for egress from the system assembled from new or modified packet data and unmodified packet data as retrieved directly from the buffer. According to a sixth aspect of the invention, a system for preventing re-ordering of packets in a packet processing system is provided. A seventh aspect of the invention involves any combination of one or more of the foregoing.
摘要翻译：提供了一种分组处理系统架构和方法。根据本发明的第一方面，为分组提供多个服务质量指示符，每个具有分配的优先级，并且使用可配置的优先级分辨率方案来选择用于分配给分组的服务质量指示符之一。根据本发明的第二方面，在系统的选定区域中使用宽数据路径，同时避免系统中广泛的数据路径的普遍利用。根据本发明的第三方面，使用一个或多个堆栈来促进分组处理。根据本发明的第四方面，分组大小确定器从分组大小确定器池分配给分组，并且在确定分组的大小之后或之后返回到分组。根据本发明的第五方面，一个数据包在其进入系统之后或之后被缓存，并且一个用于从新系统或修改的分组数据组装的用于出口的分组以及从缓冲器直接获取的未修改的分组数据。根据本发明的第六方面，提供一种用于防止分组处理系统中的分组重新排序的系统。本发明的第七方面涉及上述中的一种或多种的任意组合。

2. 发明授权

US07385984B2 Packet processing system architecture and method 有权
标题翻译：分组处理系统的架构和方法
公开(公告)号：US07385984B2
公开(公告)日：2008-06-10
申请号：US10814552
申请日：2004-03-30
申请人： David K. Parker , Erik R. Swenson , Michael M. Yip , Christopher J. Young
发明人： David K. Parker , Erik R. Swenson , Michael M. Yip , Christopher J. Young
IPC分类号： H04L12/28
CPC分类号： H04L47/2441 , H04L47/10 , H04L47/2433 , H04L47/36 , H04L49/901
摘要： A packet processing system architecture and method are provided. According to a first aspect of the invention, a plurality of quality of service indicators are provided for a packet, each with an assigned priority, and a configurable priority resolution scheme is utilized to select one of the quality of service indicators for assigning to the packet. According to a second aspect of the invention, wide data paths are utilized in selected areas of the system, while avoiding universal utilization of the wide data paths in the system. According to a third aspect of the invention, one or more stacks are utilized to facilitate packet processing. According to a fourth aspect of the invention, a packet size determiner is allocated to a packet from a pool of packet size determiners, and is returned to the pool upon or after determining the size of the packet. According to a fifth aspect of the invention, a packet is buffered upon or after ingress thereof to the system, and a packet for egress from the system assembled from new or modified packet data and unmodified packet data as retrieved directly from the buffer. According to a sixth aspect of the invention, a system for preventing re-ordering of packets in a packet processing system is provided. A seventh aspect of the invention involves any combination of one or more of the foregoing.
摘要翻译：提供了一种分组处理系统架构和方法。根据本发明的第一方面，为分组提供多个服务质量指示符，每个具有分配的优先级，并且使用可配置的优先级分辨率方案来选择用于分配给分组的服务质量指示符之一。根据本发明的第二方面，在系统的选定区域中使用宽数据路径，同时避免系统中广泛的数据路径的普遍利用。根据本发明的第三方面，使用一个或多个堆栈来促进分组处理。根据本发明的第四方面，分组大小确定器从分组大小确定器池分配给分组，并且在确定分组的大小之后或之后返回到分组。根据本发明的第五方面，一个数据包在其进入系统之后或之后被缓存，并且一个用于从新系统或修改的分组数据组装的用于出口的分组以及从缓冲器直接获取的未修改的分组数据。根据本发明的第六方面，提供一种用于防止分组处理系统中的分组重新排序的系统。本发明的第七方面涉及上述中的一种或多种的任意组合。

3. 发明授权

US07292591B2 Packet processing system architecture and method 有权
标题翻译：分组处理系统的架构和方法
公开(公告)号：US07292591B2
公开(公告)日：2007-11-06
申请号：US10814725
申请日：2004-03-30
申请人： David K. Parker , Erik R. Swenson , Michael M. Yip , Christopher J. Young
发明人： David K. Parker , Erik R. Swenson , Michael M. Yip , Christopher J. Young
IPC分类号： H04L12/28
CPC分类号： H04L69/16 , H04L47/10 , H04L47/2441 , H04L47/2458 , H04L47/31 , H04L49/90 , H04L69/161 , H04L69/22
摘要： A packet processing system architecture and method are provided. According to a first aspect of the invention, packet parser functions are distributed throughout a packet processing system comprising a packet classification system and a packet modification system. According to a second aspect of the invention, an egress mirroring function is provided to the system. According to a third aspect of the invention, a multi-dimensional quality of service indicator for a packet is provided. According to a fourth aspect of the invention, a cascaded combination of multiple, replicated packet processing systems is used to process a packet. A fifth aspect of the invention involves any combination of one or more of the foregoing.
摘要翻译：提供了一种分组处理系统架构和方法。根据本发明的第一方面，分组解析器功能分布在包括分组分类系统和分组修改系统的分组处理系统中。根据本发明的第二方面，向系统提供出口镜像功能。根据本发明的第三方面，提供了一种用于分组的多维度服务质量指示符。根据本发明的第四方面，使用多个复制分组处理系统的级联组合来处理分组。本发明的第五方面涉及一种或多种前述的任何组合。

4. 发明授权

US08161270B1 Packet data modification processor 有权
标题翻译：分组数据修改处理器
公开(公告)号：US08161270B1
公开(公告)日：2012-04-17
申请号：US10814556
申请日：2004-03-30
申请人： David K. Parker , Erik R. Swenson , Christopher J. Young
发明人： David K. Parker , Erik R. Swenson , Christopher J. Young
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3867 , G06F9/30018 , G06F9/30029 , G06F9/345 , H04L49/30
摘要： A programmable processor configured to perform one or more packet modifications through execution of one or more commands. A pipelined processor core comprises a first stage configured to selectively shift and mask data in each of a plurality of categories in response to one or more decoded commands, and combine the selectively shifted and masked data in each of the categories. The pipelined processor core further comprises a second stage configured to selectively perform one or more operations on the combined data from the first stage and other data responsive to the one or more decoded commands. In one implementation, the processor is implemented as an application specific integrated circuit (ASIC).
摘要翻译：配置为通过执行一个或多个命令来执行一个或多个分组修改的可编程处理器。流水线处理器核心包括第一级，其被配置为响应于一个或多个解码的命令来选择性地移位和屏蔽多个类别中的每一个中的数据，并且组合每个类别中的有选择地移位和屏蔽的数据。流水线处理器核心还包括第二级，其被配置为响应于一个或多个解码的命令，选择性地对来自第一级的组合数据和其他数据执行一个或多个操作。在一个实现中，处理器被实现为专用集成电路（ASIC）。

5. 发明授权

US08139583B1 Command selection in a packet forwarding device 有权
标题翻译：分组转发设备中的命令选择
公开(公告)号：US08139583B1
公开(公告)日：2012-03-20
申请号：US12242686
申请日：2008-09-30
申请人： Charles Frederick Burton, III , Christopher J. Young
发明人： Charles Frederick Burton, III , Christopher J. Young
IPC分类号： H04L12/28
CPC分类号： H04L49/3009 , H04L49/00
摘要： Packet modification is performed in the switch fabric by selecting a conditional command belonging to a set of commands for modifying a packet. The set of commands is identified based on an index value, and selecting a conditional command belonging to the set of commands is based on a mask value, where the index and mask values are determined based on data in the packet undergoing modification, such as the packet's source and destination, or incoming label. Among other advantages, controlling packet modification in the switch fabric through selecting a conditional command belonging to a set of commands allows multiple sets of commands to be replaced with a single set of commands, resulting in a more efficient use of available external memory.
摘要翻译：通过选择属于用于修改分组的一组命令的条件命令，在交换结构中执行分组修改。基于索引值来识别该组命令，并且选择属于该组命令的条件命令基于掩码值，其中根据正在进行修改的分组中的数据来确定索引和掩码值，例如数据包的来源和目的地，或传入的标签。除了其他优点之外，通过选择属于一组命令的条件命令来控制交换结构中的分组修改允许用一组命令替换多组命令，从而更有效地使用可用的外部存储器。

6. 发明授权

US07821931B2 System and method for assembling a data packet 有权
标题翻译：用于组装数据包的系统和方法
公开(公告)号：US07821931B2
公开(公告)日：2010-10-26
申请号：US11924500
申请日：2007-10-25
申请人： Erik R. Swenson , Christopher J. Young
发明人： Erik R. Swenson , Christopher J. Young
IPC分类号： H04J1/16 , H04L12/26
CPC分类号： H04L49/30 , H04L45/7453 , H04L45/7457
摘要： Disclosed is a system and method for assembling a data packet. The system can be implemented as four memory elements associated with one or more processors. The first memory element stores a sequence number and a sub-channel identifier for an incoming data packet. The second memory element stores a revised packet fragment. The third memory element stores an unrevised packet fragment. The fourth memory element stores a starting address. In the system, the starting address may be the starting address of the revised packet fragment or the unrevised packet fragment wherein the first memory element identifies portions of the fourth memory element associated with the sequence number. The one or more processors are configured to create a modified data packet by combining the unrevised packet fragments and the revised packet fragment, wherein the modified data packet is associated with the sequence number and sub-channel identifier.
摘要翻译：公开了一种用于组装数据分组的系统和方法。该系统可以被实现为与一个或多个处理器相关联的四个存储器元件。第一存储器元件存储用于输入数据分组的序列号和子信道标识符。第二存储器元件存储经修改的分组片段。第三存储器元件存储未修改的分组片段。第四存储元件存储起始地址。在系统中，起始地址可以是经修改的分组片段或未修改分组片段的起始地址，其中第一存储器元素标识与序列号相关联的第四存储器元件的部分。一个或多个处理器被配置为通过组合未修改的分组片段和经修改的分组片段来创建修改的数据分组，其中修改的数据分组与序列号和子频道标识符相关联。

7. 发明授权

US07539750B1 System and method for packet processor status monitoring 有权
标题翻译：分组处理器状态监控的系统和方法
公开(公告)号：US07539750B1
公开(公告)日：2009-05-26
申请号：US10814728
申请日：2004-03-30
申请人： David K. Parker , Erik R. Swenson , Christopher J. Young
发明人： David K. Parker , Erik R. Swenson , Christopher J. Young
IPC分类号： G06F15/16 , G06F12/00
CPC分类号： G06F15/16
摘要： Disclosed herein are a system and method for status monitoring, including debug error detection, during data packet processing. In general terms, the system for status monitoring during data packet processing can be implemented as a system including a packet processor and a buffer. The packet processor generates processing data based on one or more control structures while revising packet data. The packet processor generates the processing data while performing one or more lookup cycles. The buffer records the processing data and the status of the one or more control structures. The processing data includes a lookup number and the lookup number identifies the number of cycles performed by the packet processor.
摘要翻译：这里公开了一种用于状态监视的系统和方法，包括在数据分组处理期间的调试错误检测。一般来说，数据分组处理期间的状态监视系统可以实现为包括分组处理器和缓冲器的系统。分组处理器在修改分组数据的同时基于一个或多个控制结构生成处理数据。分组处理器在执行一个或多个查找周期时产生处理数据。缓冲器记录处理数据和一个或多个控制结构的状态。处理数据包括查找号码，查找号码标识由分组处理器执行的周期数。

8. 发明授权

US6068153A Dispensing cover for fiberboard drum 失效
标题翻译：纤维板鼓的分配盖
公开(公告)号：US6068153A
公开(公告)日：2000-05-30
申请号：US242912
申请日：1999-02-25
申请人： Christopher J. Young , Brooks R. Markert
发明人： Christopher J. Young , Brooks R. Markert
IPC分类号： B65D3/26 , B65D21/02 , B65D43/02 , B65D47/08 , B65D47/14 , B65D51/18 , B65D51/20 , B65D51/22 , B65D83/06
CPC分类号： B65D15/24 , B65D21/0222 , B65D43/021 , B65D47/0804 , B65D47/088 , B65D47/148 , B65D51/20 , B65D2251/0018 , B65D2251/0025 , B65D2251/0093 , B65D2543/00296 , B65D2543/00518 , B65D2543/00546 , B65D2543/00648 , B65D2543/00685 , B65D2543/0074 , B65D2543/00805 , B65D2543/00842
摘要： A dispensing cover (10) for use with a first fiberboard drum (14) includes a main portion (50), a skirt portion (52) and a skirt portion extension (54). The drum has a continuous upstanding drum wall (44) with a wall edge (46) having a rolled-in lip (16). The wall edge (16) forms a perimeter of a cover receiving opening (48). Main portion (50) is sized to fit within the perimeter of cover receiving opening (48). Skirt portion (52) is secured to main portion (50) and extends generally parallel to upstanding drum wall (44). Skirt portion extension (54) is secured to skirt portion (52) and forms a cavity (56) for receiving rolled-in lip (16) of drum (14). At least one barb (12) can be provided to secure cover (10) to fiberboard drum (14). A resealable lid (20) and a dispensing cover seal (30) can also be provided. The seal (30) prevents undesirable retention of product by the rolled-in lip (16). A stack alignment lip (42) can be provided to allow stacking of adjacent drums (14), (36).
摘要翻译： PCT No.PCT / US97 / 15085 Sec。一九九九年二月二十五日 102（e）1999年2月25日PCT 1997年8月27日PCT PCT。公开号WO98 / 09881 1998年3月12日，与第一纤维板鼓（14）一起使用的分配盖（10）包括主要部分（50），裙部（52）和裙部延伸部（54）。滚筒具有连续竖立的鼓壁（44），其中边缘（46）具有卷起的唇部（16）。壁边缘（16）形成盖接收开口（48）的周边。主要部分（50）的尺寸被设计成装配在盖接收开口（48）的周边内。裙部（52）固定在主体部分（50）上并且大致平行于直立鼓壁（44）延伸。裙部分延伸部分54固定在裙部52上并形成用于容纳滚筒14的卷入式唇缘16的空腔56。可以提供至少一个倒钩（12）以将盖（10）固定到纤维板鼓（14）上。还可以提供可重新密封的盖子（20）和分配盖子密封件（30）。密封件（30）防止产品被卷入的唇缘（16）的不期望的保留。可以提供堆叠对准唇缘（42）以允许相邻的滚筒（14），（36）的堆叠。

9. 发明授权

US10758940B1 Mobile sieving apparatus and method for harvesting cannabis pollen and trichomes 有权
公开(公告)号：US10758940B1
公开(公告)日：2020-09-01
申请号：US16211306
申请日：2018-12-06
申请人： Christopher J. Young
发明人： Christopher J. Young
IPC分类号： B07B1/02 , B07B1/00 , B07B1/46
摘要： A mobile sieving apparatus and method for harvesting cannabis pollen and trichomes separates the flowers of a cannabis plant. A large sieve panel, a medium sieve panel, a small sieve panel, and a silk screen panel are arranged in a spaced-apart stacked arrangement inside a harvesting vehicle. The sieved panels have different sized openings to enable passage of corresponding portions of the cannabis plant. The sieve panels are arranged by graduated separation, in which the distance between panels correlates to the size of the cannabis plant components passing through the opening. A harvesting panel has a solid, flat surface, and positions below the sieve panels to catch the pollens and trichomes falling through. The panels are stacked in a harvesting vehicle, sliding onto docking rails that slidably receive the edges of panels. The harvesting vehicle is lightweight to enable manual agitation of the vehicle, and enhance mobility of the panels.

10. 发明授权

US08924694B2 Packet data modification processor 有权
标题翻译：分组数据修改处理器
公开(公告)号：US08924694B2
公开(公告)日：2014-12-30
申请号：US13444700
申请日：2012-04-11
申请人： David K. Parker , Erik R. Swenson , Christopher J. Young
发明人： David K. Parker , Erik R. Swenson , Christopher J. Young
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3867 , G06F9/30018 , G06F9/30029 , G06F9/345 , H04L49/30
摘要： A programmable processor configured to perform one or more packet modifications through execution of one or more commands. A pipelined processor core comprises a first stage configured to selectively shift and mask data in each of a plurality of categories in response to one or more decoded commands, and combine the selectively shifted and masked data in each of the categories. The pipelined processor core further comprises a second stage configured to selectively perform one or more operations on the combined data from the first stage and other data responsive to the one or more decoded commands. In one implementation, the processor is implemented as an application specific integrated circuit (ASIC).
摘要翻译：配置为通过执行一个或多个命令来执行一个或多个分组修改的可编程处理器。流水线处理器核心包括第一级，其被配置为响应于一个或多个解码的命令来选择性地移位和屏蔽多个类别中的每一个中的数据，并且组合每个类别中的有选择地移位和屏蔽的数据。流水线处理器核心还包括第二级，其被配置为响应于一个或多个解码的命令来选择性地对来自第一级的组合数据和其他数据执行一个或多个操作。在一个实现中，处理器被实现为专用集成电路（ASIC）。

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