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1. 发明授权

US09287154B2 UV curing system for semiconductors 有权
标题翻译：半导体UV固化系统
公开(公告)号：US09287154B2
公开(公告)日：2016-03-15
申请号：US13486025
申请日：2012-06-01
申请人： Ming Huei Lien , Chia-Ho Chen , Shu-Fen Wu , Chih-Tsung Lee , You-Hua Chou
发明人： Ming Huei Lien , Chia-Ho Chen , Shu-Fen Wu , Chih-Tsung Lee , You-Hua Chou
IPC分类号： H01L21/677 , H01L21/68 , H01L21/67 , H01L21/3105
CPC分类号： H01L21/6776 , H01L21/3105 , H01L21/67115
摘要： Embodiments of an ultraviolet (UV) curing system for treating a semiconductor substrate such as a wafer are disclosed. The curing system generally includes a processing chamber, a wafer support for holding a wafer in the chamber, a UV radiation source disposed above the chamber, and a UV transparent window interspersed between the radiation source and wafer support. In one embodiment, the wafer support is provided by a belt conveyor operable to transport wafers through the chamber during UV curing. In another embodiment, the UV radiation source is a movable lamp unit that travels across the top of the chamber for irradiating the wafer. In another embodiment, the UV transparent window includes a UV radiation modifier that reduces the intensity of UV radiation on portions of the wafer positioned below the modifier. Various embodiments enhance wafer curing uniformity by normalizing UV intensity levels on the wafer.
摘要翻译：公开了用于处理诸如晶片的半导体衬底的紫外（UV）固化系统的实施例。固化系统通常包括处理室，用于在室中保持晶片的晶片支撑件，设置在室上方的UV辐射源，以及散布在辐射源和晶片支撑件之间的UV透明窗口。在一个实施例中，晶片支撑件由带式输送机提供，其可操作以在UV固化期间将晶片传送通过室。在另一个实施例中，UV辐射源是可移动的灯单元，其移动穿过室的顶部以照射晶片。在另一个实施方案中，UV透明窗口包括UV辐射调节剂，其降低位于调节剂下方的晶片部分上的UV辐射强度。各种实施例通过使晶片上的UV强度水平归一化来增强晶片固化均匀性。

2. 发明授权

US08916480B2 Chemical vapor deposition film profile uniformity control 有权
标题翻译：化学气相沉积膜轮廓均匀性控制
公开(公告)号：US08916480B2
公开(公告)日：2014-12-23
申请号：US13313106
申请日：2011-12-07
申请人： Ming-Shiou Kuo , Chih-Tsung Lee , You-Hua Chou , Ming-Chin Tsai , Chia-Ho Chen , Chin-Hsiang Lin
发明人： Ming-Shiou Kuo , Chih-Tsung Lee , You-Hua Chou , Ming-Chin Tsai , Chia-Ho Chen , Chin-Hsiang Lin
IPC分类号： H01L21/31
CPC分类号： C23C16/44 , C23C16/45565
摘要： The present disclosure provides for methods and systems for controlling profile uniformity of a chemical vapor deposition (CVD) film. A method includes depositing a first layer on a substrate by CVD with a first shower head, the first layer having a first profile, and depositing a second layer over the first layer by CVD with a second shower head, the second layer having a second profile. The combined first layer and second layer have a third profile, and the first profile, the second profile, and the third profile are different from one another.
摘要翻译：本公开提供了用于控制化学气相沉积（CVD）膜的轮廓均匀性的方法和系统。一种方法包括通过CVD用第一喷淋头沉积第一层在CVD衬底上，第一层具有第一轮廓，并且通过CVD与第二喷淋头在第一层上沉积第二层，第二层具有第二轮廓。组合的第一层和第二层具有第三轮廓，并且第一轮廓，第二轮廓和第三轮廓彼此不同。

3. 发明申请

US20130147046A1 Integrated Technology for Partial Air Gap Low K Deposition 有权
标题翻译：部分气隙低K沉积的综合技术
公开(公告)号：US20130147046A1
公开(公告)日：2013-06-13
申请号：US13313542
申请日：2011-12-07
申请人： Hung Jui Chang , Chih-Tsung Lee , You-Hua Chou , Shiu-Ko Jang Jian , Ming-Shiou Kuo
发明人： Hung Jui Chang , Chih-Tsung Lee , You-Hua Chou , Shiu-Ko Jang Jian , Ming-Shiou Kuo
IPC分类号： H01L23/48 , H01L23/538
CPC分类号： H01L21/764 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor body and a low K dielectric layer overlying the semiconductor body. A first portion of the low K dielectric layer comprises a dielectric material, and a second portion of the low K dielectric layer comprise an air gap, wherein the first portion and the second portion are laterally disposed with respect to one another. A method for forming a low K dielectric layer is also disclosed and includes forming a dielectric layer over a semiconductor body, forming a plurality of air gaps laterally disposed from one another in the dielectric layer, and forming a capping layer over the dielectric layer and air gaps.
摘要翻译：半导体器件包括半导体本体和覆盖半导体本体的低K电介质层。低K电介质层的第一部分包括电介质材料，低K电介质层的第二部分包括气隙，其中第一部分和第二部分相对于彼此横向设置。还公开了一种用于形成低K电介质层的方法，包括在半导体本体上形成电介质层，在电介质层中形成彼此横向设置的多个气隙，并在电介质层和空气上形成覆盖层差距

4. 发明授权

US07432192B2 Post ECP multi-step anneal/H2 treatment to reduce film impurity 有权
标题翻译：后期ECP多步退火/ H2处理以降低膜杂质
公开(公告)号：US07432192B2
公开(公告)日：2008-10-07
申请号：US11347946
申请日：2006-02-06
申请人： Hsien-Ping Feng , Jung-Chih Tsao , Hsi-Kuei Cheng , Chih-Tsung Lee , Ming-Yuan Cheng , Steven Lin , Ray Chuang , Chi-Wen Liu
发明人： Hsien-Ping Feng , Jung-Chih Tsao , Hsi-Kuei Cheng , Chih-Tsung Lee , Ming-Yuan Cheng , Steven Lin , Ray Chuang , Chi-Wen Liu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76877 , H01L21/2885
摘要： A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.
摘要翻译：描述了在双镶嵌方案中形成铜互连的方法。在扩散阻挡层和种子层依次形成在电介质层中的沟槽和通孔的侧壁和底部上之后，通过第一ECP工艺以10mA / cm 2 / >电流密度以填充通孔和部分沟槽。进行第一退火步骤以除去碳杂质，并且任选地包括H 2 O 3等离子体处理。使用在40mA / cm 2电流密度下的第一沉积步骤和以60mA / cm 2电流密度进行第二沉积步骤的第二个ECP工艺来沉积第二铜层超过沟槽。在第二退火步骤之后，CMP工艺使铜层平坦化。通过该方法可以实现更少的铜缺陷，降低的S，Cl和C杂质，以及Rc性能的提高。

5. 发明授权

US5965671A Modified phenolic resin toughened by poly (alkylene oxide) and preparation thereof 失效
标题翻译：通过聚（环氧烷）增韧的改性酚醛树脂及其制备
公开(公告)号：US5965671A
公开(公告)日：1999-10-12
申请号：US35486
申请日：1998-03-05
申请人： Chen-Chi Martin Ma , Hew-Der Wu , Chih-Tsung Lee
发明人： Chen-Chi Martin Ma , Hew-Der Wu , Chih-Tsung Lee
IPC分类号： C08G65/331 , C08L71/02 , G08G65/32
CPC分类号： C08G65/3317 , C08L71/02
摘要： Modified resole and novolac type phenolic resins which are toughened by poly(alkylene oxide) are disclosed. The modified resole type phenolic resin is prepared by the following steps: mixing a poly(alkylene oxide) having a weight average molecular weight of 100,000.about.8,000,000 and phenol in a weight ratio of poly(alkylene oxide): phenol=1.5:1.about.1:1 at an elevated temperature to form a glutinous mixture; mixing the glutinous mixture with an acid catalyst to obtain a viscous mixture having a relatively low viscosity compared to the glutinous mixture; and mixing the viscose mixture with a resole type phenolic resin. The modified novolac type phenolic resin is prepared by directly mixing the glutinous mixture with a liquid novolac type phenolic resin. The amount of the poly(alkylene oxide) mixed is 2.about.10 wt % based on the phenolic resin.
摘要翻译：公开了通过聚（环氧烷）增韧的改性甲阶酚醛树脂和酚醛清漆型酚醛树脂。通过以下步骤制备改性甲阶酚醛树脂：将聚（环氧烷）：苯酚= 1.5:1的重量比混合重均分子量为100,000,000,000,000,000,000的聚（环氧烷烃）：1在升高的温度下形成糯混合物; 将糯混合物与酸催化剂混合以获得与糯混合物相比具有相对低粘度的粘性混合物; 并将粘胶混合物与酚醛树脂酚醛树脂混合。通过将糯混合物与液体酚醛清漆型酚醛树脂直接混合来制备改性酚醛清漆型酚醛树脂。混合的聚（环氧烷）的量相对于酚醛树脂为2％（重量）。

6. 发明授权

US09708706B2 PVD apparatus and method with deposition chamber having multiple targets and magnets 有权
公开(公告)号：US09708706B2
公开(公告)日：2017-07-18
申请号：US13307242
申请日：2011-11-30
申请人： Chung-En Kao , Ming-Chin Tsai , You-Hua Chou , Chen-Chia Chiang , Chih-Tsung Lee , Ming-Shiou Kuo
发明人： Chung-En Kao , Ming-Chin Tsai , You-Hua Chou , Chen-Chia Chiang , Chih-Tsung Lee , Ming-Shiou Kuo
IPC分类号： C23C14/35 , H01J37/34
CPC分类号： C23C14/352 , H01J37/3405 , H01J37/3417
摘要： A thin film deposition system and method provide for multiple target assemblies that may be separately powered. Each target assembly includes a target and associated magnet or set of magnets. The disclosure provides a tunable film profile produced by multiple power sources that separately power the target arrangements. The relative amounts of power supplied to the target arrangements may be customized to provide a desired film and may be varied in time to produce a film with varied characteristics.

7. 发明授权

US09234278B2 CVD conformal vacuum/pumping guiding design 有权
标题翻译： CVD保形真空/抽吸引导设计
公开(公告)号：US09234278B2
公开(公告)日：2016-01-12
申请号：US13354545
申请日：2012-01-20
申请人： You-Hua Chou , Chih-Tsung Lee , Chia-Ho Chen , Chin-Hsiang Lin
发明人： You-Hua Chou , Chih-Tsung Lee , Chia-Ho Chen , Chin-Hsiang Lin
IPC分类号： C23C16/00 , C23C16/44 , C23C16/455
CPC分类号： C23C16/4405 , C23C16/45591
摘要： The present disclosure relates to a guiding element for guiding gas flow within a chamber. The guiding element includes a structure, one or more inlets, an outlet, and a transportation region. The one or more inlets are formed on a first side of the structure. The inlets have inlet sizes selected according to a removal rate and to mitigate gas flow variations within the chamber. The outlet is on a second side of the structure, opposite the first side of the structure. The outlet has an outlet size selected according to the removal rate. The transportation region is within the structure and couples or connects the inlets to the outlet.
摘要翻译：本公开涉及一种用于引导室内的气体流动的引导元件。引导元件包括结构，一个或多个入口，出口和运输区域。一个或多个入口形成在结构的第一侧上。入口具有根据去除速率选择的入口尺寸并减轻腔室内的气体流量变化。出口位于结构的第二侧，与结构的第一侧相对。出口具有根据去除率选择的出口尺寸。运输区域在结构内，并将进口连接或连接到出口。

8. 发明申请

US20140054653A1 TWO-STEP SHALLOW TRENCH ISOLATION (STI) PROCESS 有权
标题翻译：两步骤快速分离（STI）过程
公开(公告)号：US20140054653A1
公开(公告)日：2014-02-27
申请号：US13594254
申请日：2012-08-24
申请人： Min Hao Hong , You-Hua Chou , Chih-Tsung Lee , Shiu-Ko JangJian , Miao-Cheng Liao , Hsiang-Hsiang Ko , Chen-Ming Huang
发明人： Min Hao Hong , You-Hua Chou , Chih-Tsung Lee , Shiu-Ko JangJian , Miao-Cheng Liao , Hsiang-Hsiang Ko , Chen-Ming Huang
IPC分类号： H01L29/04 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/02538 , H01L21/02609 , H01L21/0334 , H01L21/31053 , H01L21/762 , H01L21/76232 , H01L21/823412 , H01L21/823481 , H01L29/0653 , H01L29/66477 , H01L29/66651 , H01L29/78
摘要： An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel.
摘要翻译：集成电路器件和用于制造集成电路器件的工艺。集成电路器件包括其中形成有沟槽的衬底，占据沟槽的隔离材料的第一层，在第一隔离材料层上形成的隔离材料的第二层，衬底上的外延生长的硅层，并且水平相邻第二层隔离材料，以及形成在外延生长的硅上的栅极结构，栅极结构限定沟道。

9. 发明申请

US20130320235A1 UV CURING SYSTEM FOR SEMICONDUCTORS 有权
标题翻译：用于半导体的UV固化系统
公开(公告)号：US20130320235A1
公开(公告)日：2013-12-05
申请号：US13486025
申请日：2012-06-01
申请人： Ming Huei LIEN , Chia-Ho CHEN , Shu-Fen WU , Chih-Tsung LEE , You-Hua CHOU
发明人： Ming Huei LIEN , Chia-Ho CHEN , Shu-Fen WU , Chih-Tsung LEE , You-Hua CHOU
IPC分类号： G21K5/08
CPC分类号： H01L21/6776 , H01L21/3105 , H01L21/67115
摘要： Embodiments of an ultraviolet (UV) curing system for treating a semiconductor substrate such as a wafer are disclosed. The curing system generally includes a processing chamber, a wafer support for holding a wafer in the chamber, a UV radiation source disposed above the chamber, and a UV transparent window interspersed between the radiation source and wafer support. In one embodiment, the wafer support is provided by a belt conveyor operable to transport wafers through the chamber during UV curing. In another embodiment, the UV radiation source is a movable lamp unit that travels across the top of the chamber for irradiating the wafer. In another embodiment, the UV transparent window includes a UV radiation modifier that reduces the intensity of UV radiation on portions of the wafer positioned below the modifier. Various embodiments enhance wafer curing uniformity by normalizing UV intensity levels on the wafer.
摘要翻译：公开了用于处理诸如晶片的半导体衬底的紫外（UV）固化系统的实施例。固化系统通常包括处理室，用于在室中保持晶片的晶片支撑件，设置在室上方的UV辐射源，以及散布在辐射源和晶片支撑件之间的UV透明窗口。在一个实施例中，晶片支撑件由带式输送机提供，其可操作以在UV固化期间将晶片传送通过室。在另一个实施例中，UV辐射源是可移动的灯单元，其移动穿过室的顶部以照射晶片。在另一个实施方案中，UV透明窗口包括UV辐射调节剂，其降低位于调节剂下方的晶片部分上的UV辐射强度。各种实施例通过使晶片上的UV强度水平归一化来增强晶片固化均匀性。

10. 发明申请

US20130239889A1 VALVE PURGE ASSEMBLY FOR SEMICONDUCTOR MANUFACTURING TOOLS 审中-公开
标题翻译：用于半导体制造工具的阀门组件
公开(公告)号：US20130239889A1
公开(公告)日：2013-09-19
申请号：US13419835
申请日：2012-03-14
申请人： Ming Huei LIEN , Chia-Ho CHEN , Shu-Fen WU , Chih-Tsung LEE , You-Hua CHOU
发明人： Ming Huei LIEN , Chia-Ho CHEN , Shu-Fen WU , Chih-Tsung LEE , You-Hua CHOU
IPC分类号： C23C16/00 , F24F7/00
CPC分类号： C23C16/54 , C23C16/4405 , C23C16/4408 , H01L21/67126
摘要： A semiconductor manufacturing tool and method for operating the tool are provided. The semiconductor manufacturing tool includes a process chamber in which plasma operations or ion etching operations are carried out and a valve assembly for opening and closing a valve that provides for loading and unloading substrates into and out of, the semiconductor manufacturing tool. While a processing operation is being carried out in the chamber, a valve assembly purge operation also takes place. The valve assembly purge operation involves inert gases being directed to the valve assembly area to prevent the buildup of particles and contaminating films in the valve assembly. Because the valve assembly is maintained in a clean condition, particle contamination is reduced or eliminated.
摘要翻译：提供了一种用于操作该工具的半导体制造工具和方法。半导体制造工具包括其中执行等离子体操作或离子蚀刻操作的处理室和用于打开和关闭提供用于将衬底加载和卸载到半导体制造工具中的阀的阀组件。当在腔室中进行处理操作时，也发生阀组件清洗操作。阀组件清洗操作涉及惰性气体被引导到阀组件区域，以防止阀组件中的颗粒和污染膜的积聚。因为阀组件保持在清洁状态，颗粒污染被减少或消除。

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