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1. 发明申请

US20130161816A1 SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：半导体封装
公开(公告)号：US20130161816A1
公开(公告)日：2013-06-27
申请号：US13773896
申请日：2013-02-22
申请人： Chi-Chih Chu , Cheng-Yi Weng
发明人： Chi-Chih Chu , Cheng-Yi Weng
IPC分类号： H01L23/498
CPC分类号： H01L23/3128 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/48225 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least on opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors. Whereby, the solder mask contacts the first pads directly, and thus results in higher bonding strength, so as to avoid the bridge between the first conductors caused by the first conductors permeating into the interface between the solder mask and the first pads.
摘要翻译：本发明涉及一种半导体封装。半导体封装包括衬底，至少一个芯片，多个导电元件，多个第一导体和模制化合物。基板具有多个第一焊盘和焊接掩模。第一焊盘暴露于衬底的第一表面，并且第一焊盘的材料是铜。焊接掩模设置在第一表面上，直接接触第一焊盘，并且至少具有开口以暴露第一焊盘的部分。芯片安装在基板的第一表面上。导电元件电连接芯片和基板。第一导体设置在第一焊盘上。模塑料配置在基板的第一表面上，并封装芯片，导电元件和第一导体的一部分。由此，焊接掩模直接接触第一焊盘，从而导致更高的焊接强度，以避免第一导体之间由第一导体渗入焊料掩模和第一焊盘之间的界面引起的桥。

2. 发明申请

US20100032822A1 CHIP PACKAGE STRUCTURE 审中-公开
标题翻译：芯片包装结构
公开(公告)号：US20100032822A1
公开(公告)日：2010-02-11
申请号：US12512319
申请日：2009-07-30
申请人： CHEN-KAI LIAO , CHENG-YI WENG , MENG-JEN WANG
发明人： CHEN-KAI LIAO , CHENG-YI WENG , MENG-JEN WANG
IPC分类号： H01L23/498
CPC分类号： H01L23/3128 , H01L23/49816 , H01L24/48 , H01L25/105 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2225/1023 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/10156 , H01L2924/181 , H01L2924/1815 , H01L2224/0401 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip package structure including a first substrate, a chip, a second substrate, a plurality of conductive wires, a plurality of solder balls and a molding compound is provided. The chip is disposed on the first substrate. The second substrate disposed on the chip has an upper surface and a lower surface, in which a distance of the lower surface relative to the chip is smaller than that of the upper surface relative to the chip. The upper surface has a ball mounting surface and a wire bonding surface. A distance between the wire bonding surface and the first substrate is smaller than that between the ball mounting surface and the first substrate. The conductive wires connect the wire bonding surface to the first substrate. The solder balls are disposed on the ball mounting surface. The molding compound is disposed on the first substrate.
摘要翻译：提供了包括第一基板，芯片，第二基板，多个导线，多个焊球和模制化合物的芯片封装结构。芯片设置在第一基板上。设置在芯片上的第二基板具有上表面和下表面，下表面相对于芯片的距离小于上表面相对于芯片的距离。上表面具有球安装面和引线接合面。导线接合面与第一基板之间的距离小于球安装面与第一基板之间的距离。导线将引线接合表面连接到第一基板。焊球设置在球安装面上。模塑料配置在第一基板上。

3. 发明授权

US08198131B2 Stackable semiconductor device packages 有权
标题翻译：可堆叠半导体器件封装
公开(公告)号：US08198131B2
公开(公告)日：2012-06-12
申请号：US12846630
申请日：2010-07-29
申请人： Cheng-Yi Weng , Chi-Chih Chu , Chien-Yuan Tseng
发明人： Cheng-Yi Weng , Chi-Chih Chu , Chien-Yuan Tseng
IPC分类号： H01L21/02
CPC分类号： H01L24/97 , H01L21/56 , H01L21/561 , H01L23/3128 , H01L23/49816 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/105 , H01L25/50 , H01L2223/54426 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/45664 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H01L2924/00014 , H01L2224/81 , H01L2224/85 , H01L2924/00012 , H01L2924/00
摘要： Described herein are stackable semiconductor device packages and related stacked package assemblies and methods. In one embodiment, a manufacturing method includes: (1) providing a substrate including contact pads disposed adjacent to an upper surface of the substrate; (2) applying an electrically conductive material to form conductive bumps disposed adjacent to respective ones of the contact pads; (3) electrically connecting a semiconductor device to the upper surface of the substrate; (4) applying a molding material to form a molded structure covering the conductive bumps and the semiconductor device; (5) forming a set of cutting slits extending partially through the molded structure and the conductive bumps to form truncated conductive bumps; and (6) reflowing the truncated conductive bumps to form reflowed conductive bumps.
摘要翻译：这里描述的是可堆叠的半导体器件封装和相关的堆叠封装组件和方法。在一个实施例中，制造方法包括：（1）提供包括邻近衬底的上表面设置的接触焊盘的衬底; （2）施加导电材料以形成邻近相应接触焊盘设置的导电凸块; （3）将半导体器件电连接到衬底的上表面; （4）施加模塑材料以形成覆盖导电凸块和半导体器件的模制结构; （5）形成一组切割狭缝，其部分地延伸穿过模制结构和导电凸块以形成截断的导电凸块; 和（6）回流截断的导电凸块以形成回流的导电凸块。

4. 发明申请

US20100171207A1 STACKABLE SEMICONDUCTOR DEVICE PACKAGES 有权
标题翻译：堆叠式半导体器件封装
公开(公告)号：US20100171207A1
公开(公告)日：2010-07-08
申请号：US12547063
申请日：2009-08-25
申请人： Chi-Chih Shen , Jen-Chuan CHEN , Wen-Hsiung CHANG , Chi-Chih CHU , Cheng-Yi WENG
发明人： Chi-Chih Shen , Jen-Chuan CHEN , Wen-Hsiung CHANG , Chi-Chih CHU , Cheng-Yi WENG
IPC分类号： H01L25/11 , H01L21/56
CPC分类号： H01L21/565 , H01L21/4853 , H01L23/3128 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/45664 , H01L2224/48091 , H01L2224/48145 , H01L2224/48225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/97 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/0401 , H01L2224/45015 , H01L2924/207
摘要： In one embodiment, a manufacturing method includes: (1) applying a first electrically conductive material to an upper surface of a substrate to form first conductive bumps; (2) electrically connecting a semiconductor device to the upper surface of the substrate; (3) applying a molding material to form a molded structure covering the first conductive bumps and the semiconductor device, upper ends of the first conductive bumps being recessed below an upper surface of the molded structure; (4) forming openings adjacent to the upper surface of the molded structure, the openings exposing the upper ends of the first conductive bumps; (5) applying, through the openings, a second electrically conductive material to form second conductive bumps; and (6) forming cutting slits extending through the molded structure and the substrate.
摘要翻译：在一个实施例中，制造方法包括：（1）将第一导电材料施加到衬底的上表面以形成第一导电凸块; （2）将半导体器件电连接到衬底的上表面; （3）施加模塑材料以形成覆盖所述第一导电凸块和所述半导体器件的模制结构，所述第一导电凸块的上端在所述模制结构的上表面下方凹入; （4）形成与模制结构的上表面相邻的开口，所述开口暴露第一导电凸块的上端; （5）通过所述开口施加第二导电材料以形成第二导电凸块; 和（6）形成延伸穿过模制结构和基底的切割狭缝。

5. 发明申请

US20100133675A1 PACKAGE-ON-PACKAGE DEVICE, SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：封装封装器件，半导体封装及其制造方法
公开(公告)号：US20100133675A1
公开(公告)日：2010-06-03
申请号：US12565501
申请日：2009-09-23
申请人： Lin Wang Yu , Cheng Yi Weng
发明人： Lin Wang Yu , Cheng Yi Weng
IPC分类号： H01L23/52 , H01L21/50 , H01L23/48
CPC分类号： H01L23/49833 , H01L23/3128 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06575 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19107 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a substrate, a chip, an interposer and a molding compound. The chip is electrically connected to the upper surface of the substrate. The interposer is disposed on the chip, and electrically connected to the upper surface of the substrate. The interposer includes an embedded component and a plurality of electric contacts, wherein the embedded component is located between the upper and lower surfaces of the interposer, and the electric contacts are located on the upper surface of the interposer. The molding compound seals the chip and covers the upper surface of the substrate and the lower surface of the interposer.
摘要翻译：半导体封装包括基板，芯片，插入件和模塑料。芯片电连接到基板的上表面。插入器设置在芯片上，并且电连接到基板的上表面。插入器包括嵌入式部件和多个电触点，其中嵌入部件位于插入件的上表面和下表面之间，并且电触点位于插入器的上表面上。模塑料密封芯片并覆盖基板的上表面和插入件的下表面。

6. 发明授权

US08405212B2 Semiconductor package 有权
标题翻译：半导体封装
公开(公告)号：US08405212B2
公开(公告)日：2013-03-26
申请号：US12818422
申请日：2010-06-18
申请人： Chi-Chih Chu , Cheng-Yi Weng
发明人： Chi-Chih Chu , Cheng-Yi Weng
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/3128 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/48225 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least one opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors. Whereby, the solder mask contacts the first pads directly, and thus results in higher bonding strength, so as to avoid the bridge between the first conductors caused by the first conductors permeating into the interface between the solder mask and the first pads.
摘要翻译：本发明涉及半导体封装。半导体封装包括衬底，至少一个芯片，多个导电元件，多个第一导体和模制化合物。基板具有多个第一焊盘和焊接掩模。第一焊盘暴露于衬底的第一表面，并且第一焊盘的材料是铜。焊接掩模设置在第一表面上，直接接触第一焊盘，并且具有至少一个开口以暴露第一焊盘的部分。芯片安装在基板的第一表面上。导电元件电连接芯片和基板。第一导体设置在第一焊盘上。模塑料配置在基板的第一表面上，并封装芯片，导电元件和第一导体的一部分。由此，焊接掩模直接接触第一焊盘，从而导致更高的焊接强度，以避免第一导体之间由第一导体渗入焊料掩模和第一焊盘之间的界面引起的桥。

7. 发明申请

US20120104607A1 STACKED SEMICONDUCTOR PACKAGES AND RELATED METHODS 有权
标题翻译：堆叠半导体封装及相关方法
公开(公告)号：US20120104607A1
公开(公告)日：2012-05-03
申请号：US13246408
申请日：2011-09-27
申请人： Cheng-Yi Weng
发明人： Cheng-Yi Weng
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L23/3128 , H01L21/563 , H01L23/24 , H01L23/49811 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/01087 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/3511 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： The present stacked semiconductor packages include a bottom package and a top package. The bottom package includes a substrate, a solder mask layer, a plurality of conductive pillars and a die electrically connected to the substrate. The solder mask layer has a plurality of openings exposing a plurality of pads on the substrate. The conductive pillars are disposed on at least a portion of the pads, and protrude from the solder mask layer.
摘要翻译：本发明的堆叠半导体封装包括底部封装和顶部封装。底部封装包括衬底，焊接掩模层，多个导电柱和与衬底电连接的管芯。焊接掩模层具有暴露衬底上的多个焊盘的多个开口。导电柱设置在焊盘的至少一部分上，并从焊接掩模层突出。

8. 发明授权

US08076765B2 Stackable semiconductor device packages including openings partially exposing connecting elements, conductive bumps, or conductive conductors 有权
标题翻译：可堆叠的半导体器件封装包括部分地暴露连接元件，导电凸块或导电导体的开口
公开(公告)号：US08076765B2
公开(公告)日：2011-12-13
申请号：US12507305
申请日：2009-07-22
申请人： Kuang-Hsiung Chen , Chi-Chih Shen , Jen-Chuan Chen , Wen-Hsiung Chang , Hui-Shan Chang , Pei-Yu Hsu , Fa-Hao Wu , Chen-Yu Chia , Chi-Chih Chu , Cheng-Yi Weng , Ya-Wen Hsu
发明人： Kuang-Hsiung Chen , Chi-Chih Shen , Jen-Chuan Chen , Wen-Hsiung Chang , Hui-Shan Chang , Pei-Yu Hsu , Fa-Hao Wu , Chen-Yu Chia , Chi-Chih Chu , Cheng-Yi Weng , Ya-Wen Hsu
IPC分类号： H01L21/44 , H01L21/302 , H01L21/461
CPC分类号： H01L23/3128 , H01L21/565 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/45664 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H01L2924/00012 , H01L2224/85 , H01L2924/00 , H01L2224/0401 , H01L2224/45015 , H01L2924/207
摘要： In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width WC, and at least one of the openings has a width WU adjacent to an upper surface of the package body, such that WU>WC.
摘要翻译：在一个实施例中，半导体器件封装包括：（1）衬底单元; （2）连接元件，其邻近所述基板单元的周边设置并从所述基板单元的上表面向上延伸; （3）半导体器件，与所述衬底单元的上表面相邻并且电连接到所述衬底单元; 和（4）与衬底单元的上表面相邻并且覆盖半导体器件的封装体。封装主体的侧表面基本上与衬底单元的侧表面对准。包装体限定了至少部分地暴露相应的连接元件的开口。连接元件中的至少一个具有宽度WC，并且至少一个开口具有与封装主体的上表面相邻的宽度WU，使得WU> WC。

9. 发明申请

US20110156251A1 Semiconductor Package 有权
标题翻译：半导体封装
公开(公告)号：US20110156251A1
公开(公告)日：2011-06-30
申请号：US12818422
申请日：2010-06-18
申请人： Chi-Chih Chu , Cheng-Yi Weng
发明人： Chi-Chih Chu , Cheng-Yi Weng
IPC分类号： H01L23/485
CPC分类号： H01L23/3128 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/48225 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least one opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors. Whereby, the solder mask contacts the first pads directly, and thus results in higher bonding strength, so as to avoid the bridge between the first conductors caused by the first conductors permeating into the interface between the solder mask and the first pads.
摘要翻译：本发明涉及半导体封装。半导体封装包括衬底，至少一个芯片，多个导电元件，多个第一导体和模制化合物。基板具有多个第一焊盘和焊接掩模。第一焊盘暴露于衬底的第一表面，并且第一焊盘的材料是铜。焊接掩模设置在第一表面上，直接接触第一焊盘，并且具有至少一个开口以暴露第一焊盘的部分。芯片安装在基板的第一表面上。导电元件电连接芯片和基板。第一导体设置在第一焊盘上。模塑料配置在基板的第一表面上，并封装芯片，导电元件和第一导体的一部分。由此，焊接掩模直接接触第一焊盘，从而导致更高的焊接强度，以避免第一导体之间由第一导体渗入焊料掩模和第一焊盘之间的界面引起的桥。

10. 发明授权

US08569885B2 Stacked semiconductor packages and related methods 有权
标题翻译：堆叠式半导体封装及相关方法
公开(公告)号：US08569885B2
公开(公告)日：2013-10-29
申请号：US13246408
申请日：2011-09-27
申请人： Cheng-Yi Weng
发明人： Cheng-Yi Weng
IPC分类号： H01L23/48 , H01L23/02
CPC分类号： H01L23/3128 , H01L21/563 , H01L23/24 , H01L23/49811 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/01087 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/3511 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： The present stacked semiconductor packages include a bottom package and a top package. The bottom package includes a substrate, a solder mask layer, a plurality of conductive pillars and a die electrically connected to the substrate. The solder mask layer has a plurality of openings exposing a plurality of pads on the substrate. The conductive pillars are disposed on at least a portion of the pads, and protrude from the solder mask layer.
摘要翻译：本发明的堆叠半导体封装包括底部封装和顶部封装。底部封装包括衬底，焊接掩模层，多个导电柱和与衬底电连接的管芯。焊接掩模层具有暴露衬底上的多个焊盘的多个开口。导电柱设置在焊盘的至少一部分上，并从焊接掩模层突出。

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