专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07863121B2 Method for fabricating Schottky barrier tunnel transistor 失效
标题翻译：制造肖特基势垒隧道晶体管的方法
公开(公告)号：US07863121B2
公开(公告)日：2011-01-04
申请号：US11800914
申请日：2007-05-08
申请人： Moon-Gyu Jang , Yark-Yeon Kim , Chel-Jong Choi , Myung-Sim Jun , Tae-Youb Kim , Seong-Jae Lee
发明人： Moon-Gyu Jang , Yark-Yeon Kim , Chel-Jong Choi , Myung-Sim Jun , Tae-Youb Kim , Seong-Jae Lee
IPC分类号： H01L21/338
CPC分类号： H01L29/8126 , H01L29/66409
摘要： A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the gate electrode.
摘要翻译：肖特基势垒隧道晶体管包括栅极电极和源极和漏极区域。栅电极形成在衬底的沟道区上，以与衬底形成肖特基结。源极和漏极区域形成在暴露于栅电极两侧的衬底中。

2. 发明授权

US07713826B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07713826B2
公开(公告)日：2010-05-11
申请号：US12045797
申请日：2008-03-11
申请人： Chel Jong Choi , Moon Gyu Jang , Yark Yeon Kim , Myung Sim Jun , Tae Youb Kim
发明人： Chel Jong Choi , Moon Gyu Jang , Yark Yeon Kim , Myung Sim Jun , Tae Youb Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/28229 , H01L21/28079 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： Provided is a method of manufacturing a semiconductor device including a high-k dielectric thin layer formed using an interfacial reaction. The method includes the steps of: forming an oxide layer on a silicon substrate; depositing a metal layer on the oxide layer to form a metal silicate layer using an interfacial reaction between the oxide layer and the metal layer; forming a metal gate by etching the metal silicate layer and the metal layer; and forming a lightly doped drain (LDD) region and source and drain regions in the silicon substrate after forming the metal gate. In this method, a semiconductor device having high quality and performance can be manufactured by a simpler process at lower cost.
摘要翻译：提供一种制造包括使用界面反应形成的高k电介质薄层的半导体器件的方法。该方法包括以下步骤：在硅衬底上形成氧化物层; 使用氧化物层和金属层之间的界面反应，在氧化物层上沉积金属层以形成金属硅酸盐层; 通过蚀刻金属硅酸盐层和金属层形成金属栅极; 以及在形成金属栅极之后在硅衬底中形成轻掺杂漏极（LDD）区域和源极和漏极区域。在该方法中，可以通过更简单的工艺以较低的成本制造具有高品质和高性能的半导体器件。

3. 发明授权

US07569846B2 Phase-change memory device including nanowires and method of manufacturing the same 有权
标题翻译：包括纳米线的相变存储器件及其制造方法
公开(公告)号：US07569846B2
公开(公告)日：2009-08-04
申请号：US11429744
申请日：2006-05-08
申请人： Chel-jong Choi , Jong-bong Park , Tae-gyu Kim , Dong-woo Lee
发明人： Chel-jong Choi , Jong-bong Park , Tae-gyu Kim , Dong-woo Lee
IPC分类号： H01L47/00
CPC分类号： H01L45/144 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/16 , Y10S977/762
摘要： A phase-change random access memory (PRAM) device including a plurality of nanowires and a method of manufacturing the same include: a lower structure including a plurality of contact plugs; the nanowires extending into the contact plugs from surfaces defining a respective terminal end of the contact plugs; and a phase-change layer formed on top of the nanowires. Therefore, a reset or a set current consumed by the PRAM device is significantly reduced.
摘要翻译：包括多个纳米线的相变随机存取存储器（PRAM）器件及其制造方法包括：包括多个接触插塞的下部结构; 所述纳米线从限定所述接触插塞的相应末端的表面延伸到所述接触插塞中; 以及形成在纳米线顶部的相变层。因此，由PRAM器件消耗的复位或设定电流显着降低。

4. 发明申请

US20070012986A1 Phase-change memory device including nanowires and method of manufacturing the same 有权
标题翻译：包括纳米线的相变存储器件及其制造方法
公开(公告)号：US20070012986A1
公开(公告)日：2007-01-18
申请号：US11429744
申请日：2006-05-08
申请人： Chel-jong Choi , Jong-bong Park , Tae-gyu Kim , Dong-woo Lee
发明人： Chel-jong Choi , Jong-bong Park , Tae-gyu Kim , Dong-woo Lee
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L45/144 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/16 , Y10S977/762
摘要： a phase-change random access memory (PRAM) device including a plurality of nanowires and a method of manufacturing the same include: a lower structure including a plurality of contact plugs; the nanowires extending into the contact plugs from surfaces defining a respective terminal end of the contact plugs; and a phase-change layer formed on top of the nanowires. Therefore, a reset or a set current consumed by the PRAM device is significantly reduced.
摘要翻译：包括多个纳米线的相变随机存取存储器（PRAM）器件及其制造方法包括：包括多个接触插塞的下部结构; 所述纳米线从限定所述接触插塞的相应末端的表面延伸到所述接触插塞中; 以及形成在纳米线顶部的相变层。因此，由PRAM器件消耗的复位或设定电流显着降低。

5. 发明申请

US20060019471A1 Method for forming silicide nanowire 审中-公开
标题翻译：硅化物纳米线的形成方法
公开(公告)号：US20060019471A1
公开(公告)日：2006-01-26
申请号：US11100477
申请日：2005-04-07
申请人： Chel-jong Choi
发明人： Chel-jong Choi
IPC分类号： H01L21/20 , C23C16/54 , H01L21/324
CPC分类号： C23C14/16 , C23C14/48 , C23C14/5813 , C23C14/5833 , H01J1/304 , H01J9/025 , H01L21/0237 , H01L21/02381 , H01L21/02532 , H01L21/02581 , H01L21/02658 , H01L21/02672 , H01L21/28518
摘要： Methods for forming a silicon-based material layer are disclosed along with silicon-based material layers formed by the method and devices incorporating the silicon-based material layer. The method includes forming an amorphous layer on a silicon-based substrate, doping at least a region of the amorphous layer with a metal ion, and crystallizing the amorphous layer to form a plurality of crystal grains, wherein a grain boundary is between adjacent crystal grains and metal silicide is formed at the grain boundary. The formed metal silicide has nanowire dimensions.
摘要翻译：公开了形成硅基材料层的方法以及通过包含硅基材料层的方法和装置形成的硅基材料层。该方法包括在硅基衬底上形成非晶层，用金属离子至少掺杂非晶层区域，并使非晶层结晶以形成多个晶粒，其中晶界位于相邻的晶粒之间并且在晶界处形成金属硅化物。形成的金属硅化物具有纳米线尺寸。

6. 发明申请

US20090215232A1 SCHOTTKY BARRIER TUNNEL TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：肖特基BARRIER隧道晶体管及其制造方法
公开(公告)号：US20090215232A1
公开(公告)日：2009-08-27
申请号：US12434779
申请日：2009-05-04
申请人： Yark Yeon KIM , Seong Jae LEE , Moon Gyu JANG , Chel Jong CHOI , Myung Sim JUN , Byoung Chul PARK
发明人： Yark Yeon KIM , Seong Jae LEE , Moon Gyu JANG , Chel Jong CHOI , Myung Sim JUN , Byoung Chul PARK
IPC分类号： H01L21/338
CPC分类号： H01L29/47 , H01L29/458 , H01L29/4908 , H01L29/66545 , H01L29/66772 , H01L29/7839
摘要： Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.
摘要翻译：提供了一种肖特基势垒隧道晶体管及其制造方法，该晶体管能够使用在半导体 - 金属结上自然形成的肖特基隧道势垒作为隧道来最小化对肖特基势垒隧道晶体管的栅极侧壁的损坏所造成的漏电流屏障。该方法包括以下步骤：在绝缘基板上形成半导体沟道层; 在半导体沟道层上形成虚拟栅极; 在绝缘基板上的虚拟栅极的两侧形成源极和漏极; 去除虚拟门; 在去除所述伪栅极的侧壁上形成绝缘层; 并且在从其中去除虚拟栅极的空间中形成实际栅极。在使用伪栅极制造肖特基势垒隧道晶体管时，可以形成高k电介质栅极绝缘层和金属栅极，并且可以获得具有非常强反应性的金属层的硅化物的稳定特性。

7. 发明授权

US07545000B2 Schottky barrier tunnel transistor and method of manufacturing the same 有权
标题翻译：肖特基势垒隧道晶体管及其制造方法
公开(公告)号：US07545000B2
公开(公告)日：2009-06-09
申请号：US11485837
申请日：2006-07-13
申请人： Yark Yeon Kim , Seong Jae Lee , Moon Gyu Jang , Chel Jong Choi , Myung Sim Jun , Byoung Chul Park
发明人： Yark Yeon Kim , Seong Jae Lee , Moon Gyu Jang , Chel Jong Choi , Myung Sim Jun , Byoung Chul Park
IPC分类号： H01L27/01
CPC分类号： H01L29/47 , H01L29/458 , H01L29/4908 , H01L29/66545 , H01L29/66772 , H01L29/7839
摘要： Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.
摘要翻译：提供了一种肖特基势垒隧道晶体管及其制造方法，该晶体管能够使用在半导体 - 金属结上自然形成的肖特基隧道势垒作为隧道，将肖特基势垒隧道晶体管的栅极侧壁损坏所造成的漏电流减到最小屏障。该方法包括以下步骤：在绝缘基板上形成半导体沟道层; 在半导体沟道层上形成虚拟栅极; 在绝缘基板上的虚拟栅极的两侧形成源极和漏极; 去除虚拟门; 在去除所述伪栅极的侧壁上形成绝缘层; 并且在从其中去除虚拟栅极的空间中形成实际栅极。在使用伪栅极制造肖特基势垒隧道晶体管时，可以形成高k电介质栅极绝缘层和金属栅极，并且可以获得具有非常强反应性的金属层的硅化物的稳定特性。

8. 发明申请

US20080299736A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20080299736A1
公开(公告)日：2008-12-04
申请号：US12045797
申请日：2008-03-11
申请人： Chel Jong Choi , Moon Gyu Jang , Yark Yeon Kim , Myung Sim Jun , Tae Youb Kim
发明人： Chel Jong Choi , Moon Gyu Jang , Yark Yeon Kim , Myung Sim Jun , Tae Youb Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/28229 , H01L21/28079 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： Provided is a method of manufacturing a semiconductor device including a high-k dielectric thin layer formed using an interfacial reaction. The method includes the steps of: forming an oxide layer on a silicon substrate; depositing a metal layer on the oxide layer to form a metal silicate layer using an interfacial reaction between the oxide layer and the metal layer; forming a metal gate by etching the metal silicate layer and the metal layer; and forming a lightly doped drain (LDD) region and source and drain regions in the silicon substrate after forming the metal gate. In this method, a semiconductor device having high quality and performance can be manufactured by a simpler process at lower cost.
摘要翻译：提供一种制造包括使用界面反应形成的高k电介质薄层的半导体器件的方法。该方法包括以下步骤：在硅衬底上形成氧化物层; 使用氧化物层和金属层之间的界面反应，在氧化物层上沉积金属层以形成金属硅酸盐层; 通过蚀刻金属硅酸盐层和金属层形成金属栅极; 以及在形成金属栅极之后在硅衬底中形成轻掺杂漏极（LDD）区域和源极和漏极区域。在该方法中，可以通过更简单的工艺以较低的成本制造具有高品质和高性能的半导体器件。

9. 发明授权

US07449402B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07449402B2
公开(公告)日：2008-11-11
申请号：US11336802
申请日：2006-01-23
申请人： Soo-bong Heo , Chel-jong Choi
发明人： Soo-bong Heo , Chel-jong Choi
IPC分类号： H01L21/336
CPC分类号： H01L21/02675 , H01L21/0237 , H01L21/02387 , H01L21/02488 , H01L21/02686 , H01L21/2026 , H01L21/28035 , H01L29/4916 , H01L29/665 , H01L29/66575
摘要： Provided is a method of fabricating a semiconductor device, the method including: forming an insulating layer on a single crystal substrate; etching the insulating layer in a predetermined pattern to expose the surface of the single crystal substrate; depositing an amorphous material on the insulating layer and the exposed surface of the single crystal substrate; and completely melting the amorphous material on the single crystal substrate and the insulating layer using laser annealing and crystallizing the melted amorphous material. The semiconductor device has a single crystalline silicon gate on the insulating layer.
摘要翻译：提供一种制造半导体器件的方法，所述方法包括：在单晶衬底上形成绝缘层; 以预定图案蚀刻绝缘层以暴露单晶衬底的表面; 在绝缘层和单晶衬底的暴露表面上沉积非晶材料; 并使用激光退火并使熔融的无定形材料结晶，使单晶衬底和绝缘层上的非晶材料完全熔化。半导体器件在绝缘层上具有单晶硅栅极。

10. 发明申请

US20080132049A1 METHOD FOR FABRICATING SCHOTTKY BARRIER TUNNEL TRANSISTOR 失效
标题翻译：用于制作肖特基栅栏隧道晶体管的方法
公开(公告)号：US20080132049A1
公开(公告)日：2008-06-05
申请号：US11930902
申请日：2007-10-31
申请人： Yark-Yeon KIM , Seong-Jae Lee , Moon-Gyu Jang , Tae-Youb Kim , Chel-Jong Choi , Myung-Sim Jun , Byoung-Chul Park
发明人： Yark-Yeon KIM , Seong-Jae Lee , Moon-Gyu Jang , Tae-Youb Kim , Chel-Jong Choi , Myung-Sim Jun , Byoung-Chul Park
IPC分类号： H01L21/334
CPC分类号： H01L29/78618 , H01L29/7839
摘要： Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate; b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern; c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.
摘要翻译：提供一种用于制造肖特基势垒隧道晶体管（SBTT）的方法，其可以从根本上防止由栅极电极的两个侧壁上形成的间隔物的损坏引起的栅极漏电流的产生。一种制造肖特基势垒隧道晶体管的方法，包括：a）在由支撑衬底支撑的掩埋氧化物层上形成硅图案和牺牲图案; b）在暴露于硅图案的两侧的掩埋氧化物层上形成源极/漏极区域，源极/漏极区域由金属层形成并与硅图案的两个侧壁接触; c）去除牺牲图案以暴露硅图案的顶表面; 以及d）在暴露的硅图案上形成栅极绝缘层和栅电极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式