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1. 发明申请

US20130338460A1 Wearable Device for Continuous Cardiac Monitoring 审中-公开
标题翻译：用于连续心脏监测的可佩戴装置
公开(公告)号：US20130338460A1
公开(公告)日：2013-12-19
申请号：US13803165
申请日：2013-03-14
申请人： David Da He , Charles G. Sodini , Eric Steven Winokur
发明人： David Da He , Charles G. Sodini , Eric Steven Winokur
IPC分类号： A61B5/0205 , A61B5/00 , A61B5/04 , A61B5/1455 , A61B5/0428 , A61B5/029 , A61B5/026
CPC分类号： A61B5/0205 , A61B5/0004 , A61B5/0006 , A61B5/0022 , A61B5/02125 , A61B5/024 , A61B5/0261 , A61B5/029 , A61B5/04012 , A61B5/0402 , A61B5/0428 , A61B5/08 , A61B5/11 , A61B5/1102 , A61B5/1455 , A61B5/14551 , A61B5/486 , A61B5/6823 , A61B5/6824 , A61B5/6829 , A61B2562/0219
摘要： A physiological monitor for measuring a pulsatile motion signal (MoCG) that is delayed from, but at the same rate as, the heartbeat of a user. In one embodiment, the system includes a housing configured to be worn on the body of a user; at least one MoCG sensor, within the housing, that measures a pulsatile motion signal (MoCG) that is delayed from, but at the same rate as, the heartbeat of the user; and at least one data processor that calculates, solely based on an output of the at least one MoCG sensor, at least one of (i) heart rate (HR) and activity level for the user, and (ii) respiratory rate (RR), stroke volume (SV), and cardiac output (CO) for the user. In another embodiment, the at least one data processor is within the housing.
摘要翻译：一种生理监测器，用于测量从用户的心跳延迟但以相同速率的脉动运动信号（MoCG）。在一个实施例中，该系统包括构造成佩戴在使用者身体上的壳体; 在壳体内的至少一个MoCG传感器，其测量与使用者的心跳相比延迟但以相同速率的脉动运动信号（MoCG）; 以及至少一个数据处理器，其仅基于所述至少一个MoCG传感器的输出计算用户的（i）心率（HR）和活动水平中的至少一个，以及（ii）呼吸率（RR），搏动量（SV）和心输出量（CO）。在另一实施例中，至少一个数据处理器在壳体内。

2. 发明授权

US06008703A Digital compensation for wideband modulation of a phase locked loop frequency synthesizer 失效
标题翻译：数字补偿用于宽带调制的锁相环频率合成器
公开(公告)号：US06008703A
公开(公告)日：1999-12-28
申请号：US791215
申请日：1997-01-31
申请人： Michael H. Perrott , Charles G. Sodini , Anantha P. Chandrakasan
发明人： Michael H. Perrott , Charles G. Sodini , Anantha P. Chandrakasan
IPC分类号： H03C3/09 , H03L7/197 , H04L25/03 , H04L27/12 , H04L27/20 , H03C3/00 , H03L7/18 , H03L27/12
CPC分类号： H03C3/0933 , H03C3/0925 , H03L7/1978 , H04L25/03834 , H04L27/12 , H04L27/2017
摘要： A digital compensation filtering technique is provided that enables indirect phase locked loop modulation with a digital modulation data stream having a bandwidth that exceeds, perhaps by an order of magnitude, the bandwidth characteristic of the phase locked loop. A modulation data receiver is provided for receiving from a modulation source digital input modulation data having a bandwidth that exceeds the cutoff frequency characteristic of the phase locked loop frequency response. A digital processor is coupled to the modulation data receiver for digitally processing the input modulation data to amplify modulation data at frequencies higher than the phase locked loop cutoff frequency. This digital processor is connected to the phase locked loop frequency divider to modulate the divider based on the digitally-processed input modulation data, whereby a voltage controlled oscillator of the phase locked loop is controlled to produce a modulated output carrier signal having a modulation bandwidth that exceeds the phase locked loop cutoff frequency. The digital processing of the modulation data can be implemented by adapting a digital FIR Gaussian transmit filter such that its filter characteristic reflects the intended modulation data amplification as well as enables Gaussian Frequency Shift Keyed modulation. With this implementation, no additional componentry beyond the PLL system is needed to implement the digital modulation data processing provided by the invention.
摘要翻译：提供了一种数字补偿滤波技术，其使用具有超过相位锁相环的带宽特性的带宽的数字调制数据流进行间接锁相环调制。提供了一种调制数据接收器，用于从调制源接收具有超过锁相环频率响应的截止频率特性的带宽的数字输入调制数据。数字处理器耦合到调制数据接收器，用于数字处理输入调制数据，以便在高于锁相环截止频率的频率下放大调制数据。该数字处理器连接到锁相环分频器，以基于经数字处理的输入调制数据对分频器进行调制，由此控制锁相环的压控振荡器以产生调制输出载波信号，调制带宽为超过锁相环截止频率。调制数据的数字处理可以通过适配数字FIR高斯发射滤波器来实现，使得其滤波特性反映预期的调制数据放大以及实现高斯频移键控调制。通过这种实现，不需要在PLL系统之外的附加组件来实现本发明提供的数字调制数据处理。

3. 发明授权

US07349574B1 System and method for processing non-linear image data from a digital imager 有权
标题翻译：用于从数字成像器处理非线性图像数据的系统和方法
公开(公告)号：US07349574B1
公开(公告)日：2008-03-25
申请号：US10685126
申请日：2003-10-14
申请人： Charles G. Sodini , Jason Y. Sproul , Edward T. Chang
发明人： Charles G. Sodini , Jason Y. Sproul , Edward T. Chang
IPC分类号： G06K9/00
CPC分类号： G06T5/40 , G06T5/009 , H04N5/21 , H04N5/2351 , H04N5/2353 , H04N5/35527 , H04N5/361 , H04N5/3675 , H04N5/374 , H04N9/735
摘要： A system and method process non-linear image data, still or video, from a digital imager. Noise generated by analog-to-digital converters is filtered from a pixel of digital image data. Moreover, the effects of single pixel defects in the imager are eliminated by clamping a predetermined pixel of image data within the window when the value of the predetermined pixel is greater than a maximum value of the image data of neighboring pixels or less than a minimum value of the image data of neighboring pixels. Ripples in image data are reduced by eliminating the effects of single pixel defects before filtering for crosstalk caused by electrical crosstalk between sensor elements in an imager. Dark current is removed from image data generated by an imager by subtracting a fraction of a determined dark current value from all image data generated by the imager to compensate for nonlinearities in dark current across the imager. The image data is white balanced by creating a set of scalar color adjustments from determined average color values and constraining the set of scalar adjustments to plausible lighting conditions to prevent overcompensation on images having large regions of similar hue. Lastly, utilization of a fixed set of intensity levels is optimized by remapping and restreching the image data to create new luma values for each pixel.
摘要翻译：系统和方法从数字成像器处理非线性图像数据，静止或视频。由数字转换器产生的噪声从数字图像数据的像素滤波。此外，当预定像素的值大于相邻像素的图像数据的最大值或小于最小值时，通过在窗口内夹持图像数据的预定像素来消除成像器中的单像素缺陷的影响的相邻像素的图像数据。通过在成像器中的传感器元件之间的电串扰引起的串扰过滤之前消除单像素缺陷的影响，减少图像数据中的纹波。通过从由成像器生成的所有图像数据中减去确定的暗电流值的分数来补偿由成像器产生的图像数据中的暗电流，以补偿成像器两端的暗电流的非线性。通过从确定的平均颜色值创建一组标量颜色调整并将标量调整的集合约束到合理的照明条件以防止对具有相似色调的大区域的图像的过度补偿，图像数据被白平衡。最后，通过重新映射和修复图像数据来为每个像素创建新的亮度值来优化固定的强度级的利用。

4. 发明授权

US5491803A Response resolver for associative memories and parallel processors 失效
标题翻译：关联存储器和并行处理器的响应解析器
公开(公告)号：US5491803A
公开(公告)日：1996-02-13
申请号：US431478
申请日：1995-05-01
申请人： Frederick P. Herrmann , Charles G. Sodini
发明人： Frederick P. Herrmann , Charles G. Sodini
IPC分类号： G06F13/14 , G06F13/37 , G06F7/00 , G06F9/00 , G06F9/46 , H03K19/094
CPC分类号： G06F13/37 , G06F13/14
摘要： A logic circuit for a content-addressable-memory or parallel-processor array cell implements both prioritizing and counting functions for response resolution. It includes a means for receiving from a prior cell a response-resolution token and a means for receiving the positive or negative response of the current cell to a pattern to be matched. It also includes a means for deriving as a function of the prior cell's response-resolution token a response-resolution token for the current cell that implements prioritization and counting response-resolution functions for positive or negative pattern-matching responses of the current cell. Finally, it includes a means for selecting for the current cell the appropriate response-resolution token based on the cell's positive or negative pattern-matching response and a means for sending that response-resolution token to a subsequent cell. In a preferred embodiment of the invention, the means for selecting the current cell's response-resolution token for a positive or negative pattern-matching response uses a simple pass-transistor switching circuit.
摘要翻译：用于内容寻址存储器或并行处理器阵列单元的逻辑电路实现了用于响应分辨率的优先级和计数功能。它包括用于从先前小区接收响应分辨率令牌的装置和用于将当前小区的正或负响应接收到要匹配的模式的装置。它还包括用于根据先前单元的响应分辨率令牌来导出用于对当前单元的正或负模式匹配响应进行优先级排序和计数响应分辨率函数的当前单元的响应分辨率令牌的装置。最后，它包括用于基于小区的正或负模式匹配响应为当前小区选择适当的响应分辨率令牌的装置，以及用于将该响应分辨率令牌发送到后续小区的装置。在本发明的优选实施例中，用于选择正或负模式匹配响应的当前单元的响应分辨率令牌的装置使用简单的通过晶体管切换电路。

5. 发明授权

US4831585A Four transistor cross-coupled bitline content addressable memory 失效
标题翻译：四个晶体管交叉耦合位线内容可寻址存储器
公开(公告)号：US4831585A
公开(公告)日：1989-05-16
申请号：US115585
申请日：1987-10-26
申请人： Jon P. Wade , Charles G. Sodini
发明人： Jon P. Wade , Charles G. Sodini
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： A content addressable memory cell comprises two storage IGFETs connected between a Match line and respective bitlines. Stored potentials are applied to the gates of the IGFETs through Write IGFETs which are cross coupled to the bitlines. The cross-coupling results in a larger storage capacitance and reduced degenerative capacitive coupling. This improves the speed and noise immunity of the cell. The memory cell is fabricated with three primary levels: a lower level of semiconductor material in which the source, drain and channel of each FET is formed, a center level of conductive material in which the Match and Write lines and the gates of the FETs are formed and an upper level in which the bitlines are formed. The center and lower levels are interconnected at buried contacts.
摘要翻译：内容可寻址存储器单元包括连接在匹配线和相应位线之间的两个存储IGFET。通过与交叉耦合到位线的写入IGFET将存储的电位施加到IGFET的栅极。交叉耦合导致更大的存储电容和减小的退化电容耦合。这提高了电池的速度和抗噪声能力。存储单元由三个主要级别制成：其中形成每个FET的源极，漏极和沟道的较低级别的半导体材料，导体材料的中心电平，其中匹配和写入线和FET的栅极为形成，并且形成位线的上层。中心和下层在埋地接触处相互连接。

6. 发明授权

US4799192A Three-transistor content addressable memory 失效
标题翻译：三晶体管内存可寻址存储器
公开(公告)号：US4799192A
公开(公告)日：1989-01-17
申请号：US901514
申请日：1986-08-28
申请人： Jon P. Wade , Charles G. Sodini
发明人： Jon P. Wade , Charles G. Sodini
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： A content addressable memory cell includes two storage field effect transistors of opposite conductivity type with their gates connected in common. A single write transistor is connected between the common gates and a bitline for storing a potential on the gates from the bitline.
摘要翻译：内容可寻址存储单元包括两个具有相反导电类型的存储场效应晶体管，其栅极共同连接。单个写入晶体管连接在公共栅极和位线之间，用于从位线存储栅极上的电位。

7. 发明授权

US4163243A One-transistor memory cell with enhanced capacitance 失效
标题翻译：具有增强电容的单晶体管存储单元
公开(公告)号：US4163243A
公开(公告)日：1979-07-31
申请号：US838199
申请日：1977-09-30
申请人： Theodore I. Kamins , Charles G. Sodini
发明人： Theodore I. Kamins , Charles G. Sodini
IPC分类号： G11C11/401 , G11C11/35 , G11C11/404 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78 , H01L27/04 , G11C11/24
CPC分类号： G11C11/404 , G11C11/35 , H01L27/10805
摘要： A one-transistor memory cell is provided in which the depletion-layer capacitance of an MOS capacitor is increased by locally enhancing the substrate dopant concentration. In preferred embodiments the substrate may also be doped adjacent to the substrate-insulator boundary with ions of appropriate conductivity type to form a diode junction in the substrate. The effective capacitance of the memory cell is therefore the capacitance of the insulator in parallel with the substantially increased depletion-layer or diode junction capacitance.
摘要翻译：提供了通过局部增强衬底掺杂剂浓度来增加MOS电容器的耗尽层电容的单晶体管存储单元。在优选实施例中，衬底也可以用适当导电类型的离子与衬底 - 绝缘体边界相邻地掺杂，以在衬底中形成二极管结。因此，存储器单元的有效电容是与基本上增加的耗尽层或二极管结电容并联的绝缘体的电容。

8. 发明申请

US20150257708A1 DIGITALLY ASSISTED ANALOG DYNAMIC RANGE ENHANCER 有权
标题翻译：数字辅助动态范围增强器
公开(公告)号：US20150257708A1
公开(公告)日：2015-09-17
申请号：US14320994
申请日：2014-07-01
申请人： Eric Steven Winokur , Charles G. Sodini , Tom O'Dwyer
发明人： Eric Steven Winokur , Charles G. Sodini , Tom O'Dwyer
IPC分类号： A61B5/00 , A61B5/026 , A61B5/0295 , H03K5/1252
CPC分类号： H03K5/1252 , A61B5/02427 , A61B5/7225
摘要： A circuit for expanding a dynamic range. In one embodiment, the circuit includes: a transducer generating a signal current on an output terminal in response to a physical quantity, the signal current comprising an AC current and a DC current; a dynamic range enhancement circuit having a digital control signal input terminal and producing a variable opposition current in response to a digital signal applied to the digital control signal input terminal; an amplifier; an analog to digital converter in electrical communication with the amplifier; and a digital feedback circuit in communication with the output terminal of the analog to digital converter and in electrical communication with the digital control signal input terminal of the dynamic range enhancement circuit, wherein the opposition current from the dynamic range enhancement circuit is set substantially equal to the DC current portion of the signal current from the transducer.
摘要翻译：用于扩展动态范围的电路。在一个实施例中，电路包括：响应于物理量在输出端产生信号电流的换能器，所述信号电流包括AC电流和DC电流; 具有数字控制信号输入端的动态范围增强电路，并响应于施加到数字控制信号输入端的数字信号产生可变的对立电流; 放大器与放大器电气通信的模数转换器; 以及与所述模数转换器的输出端子通信并与所述动态范围增强电路的数字控制信号输入端子电通信的数字反馈电路，其中来自所述动态范围增强电路的所述对立电流被设定为基本等于来自换能器的信号电流的直流电流部分。

9. 发明授权

US07319425B2 Comparator-based switched capacitor circuit for scaled semiconductor fabrication processes 有权
标题翻译：用于缩放半导体制造工艺的基于比较器的开关电容器电路
公开(公告)号：US07319425B2
公开(公告)日：2008-01-15
申请号：US11343064
申请日：2006-01-30
申请人： John K. Fiorenza , Todd Sepke , Hae-Seung Lee , Charles G. Sodini
发明人： John K. Fiorenza , Todd Sepke , Hae-Seung Lee , Charles G. Sodini
IPC分类号： H03M1/12
CPC分类号： H03M1/38 , H03F3/005
摘要： Described is a switched capacitor circuit for performing an analog circuit function. Unlike conventional switched capacitor circuits employing operational amplifiers, the switched capacitor circuit uses a comparator and does not require direct feedback between the input and output of the comparator. The switched capacitor circuit includes a first and a second switched capacitance network, a comparator and a current source. The first switched capacitance network has an input terminal to receive a circuit input voltage during a first phase. The comparator has an input terminal in communication with the first switched capacitance network and an output terminal in communication with the second switched capacitance network through a switched terminal. The current source communicates with the switched capacitance networks and supplies a current to charge the networks during a second phase. The circuit can be used, for example, to provide high gain amplification in integrated circuits.
摘要翻译：描述了用于执行模拟电路功能的开关电容器电路。与使用运算放大器的传统开关电容器电路不同，开关电容器电路使用比较器，并且不需要比较器的输入和输出之间的直接反馈。开关电容电路包括第一和第二开关电容网络，比较器和电流源。第一开关电容网络具有用于在第一阶段期间接收电路输入电压的输入端子。比较器具有与第一开关电容网络通信的输入端子和通过开关端子与第二开关电容网络通信的输出端子。电流源与开关电容网络通信，并在第二阶段提供电流来对网络充电。该电路可以用于例如在集成电路中提供高增益放大。

10. 发明授权

US06600471B2 Precise MOS imager transfer function control for expanded dynamic range imaging 有权
公开(公告)号：US06600471B2
公开(公告)日：2003-07-29
申请号：US09916822
申请日：2001-07-27
申请人： Hae-Seung Lee , Charles G. Sodini , Keith G. Fife
发明人： Hae-Seung Lee , Charles G. Sodini , Keith G. Fife
IPC分类号： G09G336
CPC分类号： H04N5/3765 , H04N5/35527 , H04N5/3577 , H04N5/374
摘要： There is provided an imaging system including a MOS pixel array having a number, r, of rows of pixels. Each pixel of the array includes a light detecting element, a reset node connected to the light detecting element for controlling dissipation of photogenerated charge produced by the light detecting element, and a sense node connected to the light detecting element for measuring photogenerated charge produced by the light detecting element. A charge control voltage generation circuit is provided, having a topology for producing a plurality of charge control voltages selected to control dissipation of photogenerated charge produced by the light detecting element, in accordance with a corresponding pixel transfer function. A switch circuit is connected to the voltage generation circuit and to the pixel array to apply voltages produced by the charge control voltage generation circuit to reset nodes of pixels. The application by the switch circuit of each of the charge control voltages to a row of pixel reset nodes is characterized by a voltage application settling time, tS, that is less than about 1/Nrf, where N is an integer and f is imager frame rate. This provides the ability to implement a desired transfer function, to expand imager dynamic range, in a manner that is immune to capacitances of the imager, by causing the voltage spikes, or glitches, associated with imager row capacitance, to decay substantially completely during the time over which an imager pixel row is accessed to apply a control voltage.

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