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1. 发明授权

US08399923B2 High voltage semiconductor device including field shaping layer and method of fabricating the same 有权
标题翻译：包括场成形层的高电压半导体器件及其制造方法
公开(公告)号：US08399923B2
公开(公告)日：2013-03-19
申请号：US12495948
申请日：2009-07-01
申请人： Yong-cheol Choi , Chang-ki Jeon , Min-suk Kim
发明人： Yong-cheol Choi , Chang-ki Jeon , Min-suk Kim
IPC分类号： H01L29/66
CPC分类号： H01L29/66681 , H01L29/0634 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/41758 , H01L29/42368 , H01L29/7816
摘要： Provided are a high voltage semiconductor device in which a field shaping layer is formed on the entire surface of a semiconductor substrate and a method of fabricating the same. Specifically, the high voltage semiconductor device includes a first conductivity-type semiconductor substrate. A second conductivity-type semiconductor layer is disposed on a surface of the semiconductor substrate, and a first conductivity-type body region is formed in semiconductor layer. A second conductivity-type source region is formed in the body region. A drain region is formed in the semiconductor layer and is separated from the body region. The field shaping layer is formed on the entire surface of the semiconductor layer facing the semiconductor layer.
摘要翻译：提供一种在半导体衬底的整个表面上形成场成形层的高电压半导体器件及其制造方法。具体地，高电压半导体器件包括第一导电型半导体衬底。在半导体衬底的表面上设置第二导电型半导体层，在半导体层中形成第一导电型体区。在体区域中形成第二导电型源极区域。在半导体层中形成漏区，与体区分离。在与半导体层相对的半导体层的整个表面上形成场成形层。

2. 发明授权

US08330218B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08330218B2
公开(公告)日：2012-12-11
申请号：US12870913
申请日：2010-08-30
申请人： Jong-ho Park , Hyi-Jeong Park , Hye-mi Kim , Chang-Ki Jeon
发明人： Jong-ho Park , Hyi-Jeong Park , Hye-mi Kim , Chang-Ki Jeon
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/8249 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L27/0623 , H01L27/0922 , H01L29/0653 , H01L29/41766 , H01L29/456 , H01L29/66719 , H01L29/66727 , H01L29/7809 , H01L29/7812
摘要： Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device using a DMOS device includes: a semiconductor substrate, in which a first conductive type well is formed; a first conductive type gate electrode formed on the semiconductor substrate with a gate insulating layer intervening between the gate electrode and the semiconductor substrate; a second conductive type body electrode formed on the semiconductor substrate and separated from the gate electrode; a first conductive type drain electrode formed on the semiconductor substrate and separated from the gate electrode and the body electrode; a second conductive type first body region formed in the well under the body electrode; a second conductive type second body region extending from the first body region to the gate insulating layer and formed in the well; a first conductive type source region formed in the second body region and extending from the first body region to the gate insulating layer; and a first conductive type source electrode extending from the source region to surround the gate electrode on the semiconductor substrate with an insulating layer intervening between the source electrode and gate electrode.
摘要翻译：提供半导体器件和制造半导体器件的方法。使用DMOS器件的半导体器件包括：形成第一导电型阱的半导体衬底; 形成在所述半导体衬底上的第一导电型栅极电极，所述栅极绝缘层介于所述栅电极和所述半导体衬底之间; 形成在所述半导体基板上并与所述栅电极分离的第二导电型体电极; 形成在所述半导体基板上并与所述栅电极和所述主体电极分离的第一导电型漏电极; 形成在所述体电极下方的所述阱内的第二导电型第一体区域; 第二导电类型的第二主体区域，其从所述第一主体区域延伸到所述栅极绝缘层并形成在所述阱中; 形成在所述第二主体区域中并从所述第一主体区域延伸到所述栅极绝缘层的第一导电型源极区域; 以及第一导电型源电极，其从所述源极区域延伸，以在所述半导体衬底上围绕所述栅极电极，所述绝缘层介于所述源电极和栅电极之间。

3. 发明授权

US07906828B2 High-voltage integrated circuit device including high-voltage resistant diode 有权
标题翻译：高压集成电路器件包括耐高压二极管
公开(公告)号：US07906828B2
公开(公告)日：2011-03-15
申请号：US12397426
申请日：2009-03-04
申请人： Sung-lyong Kim , Chang-ki Jeon
发明人： Sung-lyong Kim , Chang-ki Jeon
IPC分类号： H01L21/70
CPC分类号： H01L29/8611 , H01L27/0629 , H01L29/0634 , H01L29/0692 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/7816 , H01L29/868 , H01L2924/0002 , H03K17/6877 , H03K2217/0036 , H01L2924/00
摘要： A high-voltage integrated circuit includes a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage, a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a voltage that varies from the ground voltage to a high voltage, a junction termination and a first isolation region electrically isolating the low-voltage circuit region from the high-voltage circuit region, a high-voltage resistant diode formed between the low-voltage circuit region and the high-voltage circuit region, and a second isolation region surrounding the high-voltage resistant diode and electrically isolating the high-voltage resistant diode from the low-voltage circuit region and the high-voltage circuit region.
摘要翻译：高压集成电路包括：具有多个相对于接地电压工作的半导体器件的低电压电路区域，具有多个半导体器件的高电压电路区域，其相对于从接地电压到高压变化，接合端接和将低压电路区域与高压电路区域电隔离的第一隔离区域，形成在低压电路区域和低压电路区域之间的高耐压二极管高压电路区域和围绕高耐压二极管的第二隔离区域，并且将高耐压二极管与低压电路区域和高压电路区域电隔离。

4. 发明授权

US5913114A Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5913114A
公开(公告)日：1999-06-15
申请号：US7534
申请日：1998-01-15
申请人： Sun-Hak Lee , Chang-Ki Jeon , Cheol-Joong Kim
发明人： Sun-Hak Lee , Chang-Ki Jeon , Cheol-Joong Kim
IPC分类号： H01L27/06 , H01L21/8249 , H01L21/8238
CPC分类号： H01L29/66712 , H01L21/8249 , H01L29/7809 , H01L29/42368
摘要： A semiconductor device, and a method of manufacturing the same, containing a high voltage DMOS transistor, a low voltage CMOS transistor, and a bipolar transistor in a single substrate. The steps include forming an isolation layer within the substrate in an isolation region between each of a DMOS region, a CMOS region, or a bipolar region. A first oxide layer of variable thickness is formed on the substrate, a thick second oxide layer is formed on the isolation layer, and a polysilicon layer is formed on both oxide layers. The polysilicon layer is patterned to form gate patterns on the first oxide layer and resistive patterns on the second oxide layer. The gate pattern is then doped but the resistive pattern is undoped. The thickness of the first oxide layer in the DMOS region is greater than the thickness of the first oxide layer in the CMOS region.
摘要翻译：在单个基板中包含高电压DMOS晶体管，低电压CMOS晶体管和双极晶体管的半导体器件及其制造方法。这些步骤包括在DMOS区域，CMOS区域或双极区域中的每一个之间的隔离区域内在衬底内形成隔离层。在衬底上形成可变厚度的第一氧化物层，在隔离层上形成厚的第二氧化物层，并且在两个氧化物层上形成多晶硅层。图案化多晶硅层以在第一氧化物层上形成栅极图案，并在第二氧化物层上形成电阻图案。然后掺杂栅极图案，但是电阻图案是未掺杂的。 DMOS区域中的第一氧化物层的厚度大于CMOS区域中第一氧化物层的厚度。

5. 发明授权

US08217487B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08217487B2
公开(公告)日：2012-07-10
申请号：US12763689
申请日：2010-04-20
申请人： Yongcheol Choi , Chang-Ki Jeon , Minsuk Kim , Donghwan Kim
发明人： Yongcheol Choi , Chang-Ki Jeon , Minsuk Kim , Donghwan Kim
IPC分类号： H02M3/07 , H01L21/70
CPC分类号： H03K17/6871 , H03K17/063 , H03K17/567 , H03K2217/0081
摘要： Disclosed is a power semiconductor device including a bootstrap circuit. The power semiconductor device includes a high voltage unit that provides a high voltage control signal so that a high voltage is output; a low voltage unit that provides a low voltage control signal so that a ground voltage is output, and is spaced apart from the high voltage unit; a charge enable unit that is electrically connected to the low voltage unit and charges a bootstrap capacitor for supplying power to the high voltage unit when the high voltage is output, when the ground voltage is output; and a high voltage cut-off unit that cuts off the high voltage when the high voltage is output so that the high voltage is not applied to the charge enable unit, and includes a first terminal electrically connected to the charge enable unit and a second terminal electrically connected to the high voltage unit.
摘要翻译：公开了一种包括自举电路的功率半导体器件。功率半导体器件包括提供高电压控制信号以便输出高电压的高电压单元; 提供低电压控制信号以便输出接地电压并与高电压单元间隔开的低压单元; 充电使能单元，当输出所述接地电压时，电连接到所述低电压单元并对输出高电压单元的自举电容充电; 以及高压截止单元，其在输出高电压时切断高电压，使得高电压不被施加到充电使能单元，并且包括电连接到充电使能单元的第一端子和第二端子电连接到高压单元。

6. 发明授权

US08072029B2 High voltage semiconductor device with floating regions for reducing electric field concentration 有权
标题翻译：具有浮动区域的高电压半导体器件，用于降低电场浓度
公开(公告)号：US08072029B2
公开(公告)日：2011-12-06
申请号：US12013354
申请日：2008-01-11
申请人： Yong-Cheol Choi , Chang-Ki Jeon , Sang-Hyun Lee
发明人： Yong-Cheol Choi , Chang-Ki Jeon , Sang-Hyun Lee
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/0634 , H01L29/0692 , H01L29/0878 , H01L29/402 , H01L29/41775 , H01L29/42368 , H01L29/7835
摘要： A high voltage semiconductor device includes a source region of a first conductivity type having an elongated projection with two sides and a rounded tip in a semiconductor substrate. A drain region of the first conductivity type is laterally spaced from the source region in the semiconductor substrate. A gate electrode extends along the projection of the source region on the semiconductor substrate between the source and drain regions. Top floating regions of a second conductivity type are disposed between the source and drain regions in the shape of arched stripes extending along the rounded tip of the projection of the source region. The top floating regions are laterally spaced from one another by regions of the first conductivity type to thereby form alternating P-N regions along the lateral dimension.
摘要翻译：高电压半导体器件包括第一导电类型的源极区域，其具有两侧的细长突起和半导体衬底中的圆形尖端。第一导电类型的漏极区域与半导体衬底中的源极区域横向间隔开。栅电极沿着半导体衬底上的源极区域的源极和漏极区域的突出部分延伸。第二导电类型的顶部浮动区域设置在沿着源极区域的投影的圆形尖端延伸的弓形条形状的源极和漏极区域之间。顶部浮动区域通过第一导电类型的区域彼此横向间隔开，从而沿横向尺寸形成交替的P-N区域。

7. 发明申请

US20090243696A1 HIGH VOLTAGE SEMICONDUCTOR DEVICE HAVING SHIFTERS AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有变形器的高电压半导体器件及其制造方法
公开(公告)号：US20090243696A1
公开(公告)日：2009-10-01
申请号：US12402528
申请日：2009-03-12
申请人： Chang-ki Jeon , Min-suk Kim , Yong-cheol Choi
发明人： Chang-ki Jeon , Min-suk Kim , Yong-cheol Choi
IPC分类号： H03L5/00 , H01L21/76
CPC分类号： H01L27/088 , H01L21/823481
摘要： Provided are a high-voltage semiconductor device including a junction termination which electrically isolates a low voltage unit from a high voltage unit, and a method of fabricating the same. The high voltage semiconductor device includes a high voltage unit, a low voltage unit surrounding the high voltage unit, and a junction termination formed between the high voltage unit and the low voltage unit and surrounding the high voltage unit to electrically isolate the high voltage unit from the low voltage unit. The junction termination includes at least one level shifter which level shifts signals from the low voltage unit and supplies the same to the high voltage unit, a first device isolation region surrounding the high voltage unit to electrically isolate the high voltage unit from the level shifter, and a resistor layer electrically connecting neighboring level shifters.
摘要翻译：提供一种包括将低电压单元与高电压单元电隔离的接合端子的高压半导体器件及其制造方法。高电压半导体器件包括高电压单元，围绕高电压单元的低电压单元，以及形成在高电压单元和低电压单元之间并且围绕高电压单元的连接端子，以将高压单元与低压单位。所述连接终端包括至少一个电平移位器，其将来自所述低电压单元的信号电平移位并将其提供给所述高压单元;围绕所述高压单元的第一器件隔离区，以将所述高压单元与所述电平移位器电隔离; 以及电连接相邻电平移位器的电阻层。

8. 发明授权

US07518209B2 Isolation of a high-voltage diode between a high-voltage region and a low-voltage region of an integrated circuit 有权
标题翻译：在集成电路的高电压区域和低电压区域之间隔离高压二极管
公开(公告)号：US07518209B2
公开(公告)日：2009-04-14
申请号：US11378210
申请日：2006-03-16
申请人： Sung-lyong Kim , Chang-ki Jeon
发明人： Sung-lyong Kim , Chang-ki Jeon
IPC分类号： H01L29/93 , H01L23/58
CPC分类号： H01L29/8611 , H01L27/0629 , H01L29/0634 , H01L29/0692 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/7816 , H01L29/868 , H01L2924/0002 , H03K17/6877 , H03K2217/0036 , H01L2924/00
摘要： Provided is a high-voltage integrated circuit device including a high-voltage resistant diode. The device includes a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage, a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a voltage that varies from the ground voltage to a high voltage, a junction termination and a first isolation region electrically isolating the low-voltage circuit region from the high-voltage circuit region, a high-voltage resistant diode formed between the low-voltage circuit region and the high-voltage circuit region, and a second isolation region surrounding the high-voltage resistant diode and electrically isolating the high-voltage resistant diode from the low-voltage circuit region and the high-voltage circuit region. Therefore, a leakage current of the high-voltage resistant diode can be prevented.
摘要翻译：提供一种包括耐高压二极管的高压集成电路装置。该器件包括具有多个相对于接地电压工作的多个半导体器件的低电压电路区域，具有多个半导体器件的高电压电路区域，其相对于从地面变化的电压工作电压到高电压，接合端接和将低压电路区域与高压电路区域电隔离的第一隔离区域，形成在低压电路区域和高压电路之间的高耐压二极管以及围绕所述耐高压二极管的第二隔离区域，并且将所述耐高压二极管与所述低压电路区域和所述高压电路区域电隔离。因此，可以防止高耐压二极管的漏电流。

9. 发明申请

US20080074165A1 HIGH VOLTAGE GATE DRIVER INTEGRATED CIRCUIT INCLUDING HIGH VOLTAGE JUNCTION CAPACITOR AND HIGH VOLTAGE LDMOS TRANSISTOR 有权
标题翻译：高压栅驱动器集成电路，包括高压连接电容器和高电压LDMOS晶体管
公开(公告)号：US20080074165A1
公开(公告)日：2008-03-27
申请号：US11950959
申请日：2007-12-05
申请人： Chang-Ki Jeon , Sung-Iyong Kim , Tae-hun kwon
发明人： Chang-Ki Jeon , Sung-Iyong Kim , Tae-hun kwon
IPC分类号： H03L5/00
CPC分类号： H01L29/7816 , H01L27/0629 , H01L29/0615 , H01L29/0696 , H01L29/0878 , H01L29/7823
摘要： There is provided a high voltage gate driver integrated circuit. The high voltage gate driver integrated circuit includes: a high voltage region; a junction termination region surrounding the high voltage region; a low voltage region surrounding the junction termination region; a level shift transistor disposed between the high voltage region and the low voltage region, at least some portions of the level shift transistor being overlapped with the junction termination region; and/or a high voltage junction capacitor disposed between the high voltage region and the low voltage region, at least some portions of the high voltage junction capacitor being overlapped with the junction termination region.
摘要翻译：提供了高压栅极驱动器集成电路。高压栅极驱动器集成电路包括：高电压区域; 围绕高电压区域的接合端接区域; 围绕所述连接端接区域的低电压区域; 设置在所述高电压区域和所述低电压区域之间的电平移位晶体管，所述电平移位晶体管的至少一些部分与所述连接终止区域重叠; 和/或设置在高电压区域和低电压区域之间的高压结电容器，高压结电容器的至少一些部分与接合端接区域重叠。

10. 发明授权

US07309894B2 High voltage gate driver integrated circuit including high voltage junction capacitor and high voltage LDMOS transistor 有权
标题翻译：高压栅极驱动器集成电路包括高压结电容和高压LDMOS晶体管
公开(公告)号：US07309894B2
公开(公告)日：2007-12-18
申请号：US11114693
申请日：2005-04-26
申请人： Chang-ki Jeon , Sung-lyong Kim , Tae-hun Kwon
发明人： Chang-ki Jeon , Sung-lyong Kim , Tae-hun Kwon
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/7816 , H01L27/0629 , H01L29/0615 , H01L29/0696 , H01L29/0878 , H01L29/7823
摘要： There is provided a high voltage gate driver integrated circuit. The high voltage gate driver integrated circuit includes: a high voltage region; a junction termination region surrounding the high voltage region; a low voltage region surrounding the junction termination region; a level shift transistor disposed between the high voltage region and the low voltage region, at least some portions of the level shift transistor being overlapped with the junction termination region; and/or a high voltage junction capacitor disposed between the high voltage region and the low voltage region, at least some portions of the high voltage junction capacitor being overlapped with the junction termination region.
摘要翻译：提供了高压栅极驱动器集成电路。高压栅极驱动器集成电路包括：高电压区域; 围绕高电压区域的接合端接区域; 围绕所述连接端接区域的低电压区域; 设置在所述高电压区域和所述低电压区域之间的电平移位晶体管，所述电平移位晶体管的至少一些部分与所述连接终止区域重叠; 和/或设置在高电压区域和低电压区域之间的高压结电容器，高压结电容器的至少一些部分与接合端接区域重叠。

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