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1. 发明授权

US06850561B1 Predictable updating of a baud divisor of an asynchronous serial port during data reception 有权
标题翻译：在数据接收期间可异步串行端口的波特除数的可预测的更新
公开(公告)号：US06850561B1
公开(公告)日：2005-02-01
申请号：US09590353
申请日：2000-06-08
申请人： Melanie D. Typaldos , Bruce A. Loyer , Hock-Koon Lee
发明人： Melanie D. Typaldos , Bruce A. Loyer , Hock-Koon Lee
IPC分类号： H04L25/45 , H04B3/46 , H04L23/00
CPC分类号： H04L25/45
摘要： A microcontroller employs an asynchronous serial port for predictably updating a baud divisor during data reception. A write enable to the baud counter ensures that the current value of the baud count in the baud counter is greater than a predetermined number of clocks so that the working baud divisor to be loaded from the working baud divisor register is stabilized. The working baud divisor register is updated during data reception by the serial port by a software write to a visible baud divisor register provided the working baud divisor in the working baud divisor register is not being used to load the baud counter. A working baud divisor register thereby maintains a value guaranteed to be stable by the time a baud counter needs to be reloaded. A visible baud divisor register and the baud counter can be on different, possibly asynchronous clocks.
摘要翻译：微控制器采用异步串行端口在数据接收期间可预测地更新波特除数。对波特率计数器的写使能可确保波特率计数器当前的波特率值大于预定数量的时钟，从而工作波特率寄存器中加载的工作波特率被稳定。如果工作波特率寄存器中的工作波特除数未用于加载波特率计数器，则工作波特率寄存器在数据接收期间通过软件写入可见波特率除数寄存器进行更新。一个工作波特除数寄存器因此在保持波特率计数器需要重新加载的时间内保持一个保证稳定的值。可见波特除数寄存器和波特率计数器可以在不同的可能的异步时钟上。

2. 发明授权

US06642742B1 Method and apparatus for controlling output impedance 有权
标题翻译：用于控制输出阻抗的方法和装置
公开(公告)号：US06642742B1
公开(公告)日：2003-11-04
申请号：US10103266
申请日：2002-03-21
申请人： Bruce A. Loyer
发明人： Bruce A. Loyer
IPC分类号： H03K1716
CPC分类号： H03K19/0005 , H03K17/164
摘要： A method and apparatus for controlling output impedance of an input/output (I/O) circuit. In one embodiment, an I/O circuit includes a first plurality of resistive elements connected in parallel and a second plurality of resistive elements connected in parallel. Each of the resistive elements includes a control terminal. The control terminal may be used to activate or deactivate the resistive element. The control terminal for each resistive element may be controlled by a control circuit, which may be configured to activate one or more of the resistive elements. Each of the resistive elements of the first plurality may be of substantially different resistances, as may be true with the second plurality of resistive elements. Due to the substantially different resistances of each of the first and second pluralities of resistive elements, the resistive step sizes for the I/O circuit remain substantially equal as additional resistive elements are activated.
摘要翻译：一种用于控制输入/输出（I / O）电路的输出阻抗的方法和装置。在一个实施例中，I / O电路包括并联连接的第一多个电阻元件和并联连接的第二多个电阻元件。每个电阻元件包括控制端子。控制端子可用于激活或去激活电阻元件。每个电阻元件的控制端可以由控制电路来控制，该控制电路可被配置成激活一个或多个电阻元件。第一多个电阻元件中的每个电阻元件可以具有基本上不同的电阻，对于第二多个电阻元件可能是这样。由于第一和第二多个电阻元件中的每个电阻元件的电阻基本上不同，因此附加电阻元件被激活时，I / O电路的电阻步长大致相等。

3. 发明授权

US06266715B1 Universal serial bus controller with a direct memory access mode 失效
标题翻译：通用串行总线控制器，具有直接存储器访问模式
公开(公告)号：US06266715B1
公开(公告)日：2001-07-24
申请号：US09088346
申请日：1998-06-01
申请人： Bruce A. Loyer , Daniel B. Reents , Allen B. Thor
发明人： Bruce A. Loyer , Daniel B. Reents , Allen B. Thor
IPC分类号： G06F1300
CPC分类号： G06F13/28
摘要： A universal serial bus (USB) device or host provides a universal serial bus (USB) controller with a direct memory access (DMA) mode. In a DMA mode, a universal serial bus (USB) transmit endpoint may be programmed for a direct memory access (DMA) transmit channel, or a universal serial bus (USB) receive endpoint may be programmed for a direct memory access (DMA) receive channel. For a USB device, a DMA transmit channel performs data transfer to a universal serial bus (USB) host, and a DMA receive channel handles data transfer from the USB host. For a USB host, a DMA transmit channel performs data transfer to the USB device, and a DMA receive channel handles data transfer from the USB device. A universal serial bus transmit protocol and a universal serial bus receive protocol for the DMA mode of the USB controller permit a maximum packet size of universal serial bus (USB) data to be programmed to a value greater than the physical size of a USB transmit or receive buffer of a USB transmit or receive endpoint. A USB controller with a DMA mode thus allows for a significant reduction in the buffer size of a USB transmit or receive buffer. A USB device having a controller with a DMA mode handles USB data as fast as the USB host can request USB data.
摘要翻译：通用串行总线（USB）设备或主机提供具有直接存储器访问（DMA）模式的通用串行总线（USB）控制器。在DMA模式下，通用串行总线（USB）传输端点可以被编程用于直接存储器访问（DMA）传输通道，或者通用串行总线（USB）接收端点可以被编程用于直接存储器访问（DMA）接收渠道。对于USB设备，DMA传输通道执行到通用串行总线（USB）主机的数据传输，DMA接收通道可以处理USB主机的数据传输。对于USB主机，DMA传输通道执行到USB设备的数据传输，DMA接收通道可以处理USB设备的数据传输。 USB控制器的DMA模式的通用串行总线传输协议和通用串行总线接收协议允许将通用串行总线（USB）数据的最大数据包大小编程为大于USB传输的物理尺寸接收USB发送或接收端点的缓冲区。因此，具有DMA模式的USB控制器可以显着降低USB发送或接收缓冲区的缓冲区大小。具有DMA模式的控制器的USB设备可以像USB主机请求USB数据那样快速处理USB数据。

4. 发明授权

US5418786A Asynchronous transfer mode (ATM) method and apparatus for communicating status bytes in a manner compatible with the utopia protocol 失效
标题翻译：用于以与乌托邦协议兼容的方式传送状态字节的异步传输模式（ATM）方法和装置
公开(公告)号：US5418786A
公开(公告)日：1995-05-23
申请号：US261513
申请日：1994-06-17
申请人： Bruce a. Loyer , Yaron Ben-Arie
发明人： Bruce a. Loyer , Yaron Ben-Arie
IPC分类号： H04L12/56 , H04Q11/04 , H04L29/10
CPC分类号： H04Q11/0478 , H04L2012/563
摘要： An asynchronous transfer mode (ATM) layer (10) is coupled to one or more physical layers (PHY layer) (12) via a plurality of conductors (14 and 16). The conductors (14 and 16) allow bi-directional communication of ATM data cells between the layers (10 and 12) using the UTOPIA protocol. In addition, the ATM layer (10) and the PHY layer (12) can communicate one or more status bytes and one or more physical identification (PHY ID) bytes to each other prior to the communication of an ATM data cell. This addition of the communication of one or more status bytes and one or more physical identification (PHY ID) bytes is fully compatible with the currently accepted UTOPIA standard and therefore adds new ATM functionality without compromising the widely-accepted UTOPIA standard for ATM.
摘要翻译：异步传输模式（ATM）层（10）经由多个导体（14和16）耦合到一个或多个物理层（PHY层）（12）。导体（14和16）允许使用UTOPIA协议在层（10和12）之间进行ATM数据单元的双向通信。此外，ATM层（10）和PHY层（12）可以在ATM数据单元通信之前将一个或多个状态字节和一个或多个物理标识（PHY ID）字节传送给彼此。一个或多个状态字节和一个或多个物理标识（PHY ID）字节的通信的这种添加与当前接受的UTOPIA标准完全兼容，因此添加新的ATM功能而不损害广泛接受的用于ATM的UTOPIA标准。

5. 发明授权

US4700185A Request with response mechanism and method for a local area network controller 失效
标题翻译：请求与局域网控制器的响应机制和方法
公开(公告)号：US4700185A
公开(公告)日：1987-10-13
申请号：US686352
申请日：1984-12-26
申请人： Thomas J. Balph , Bruce A. Loyer
发明人： Thomas J. Balph , Bruce A. Loyer
IPC分类号： G06F13/12 , G06F13/42 , H04L12/417 , H04J3/02
CPC分类号： H04L12/417 , G06F13/128 , G06F13/4208
摘要： A request with response mechanism and method for a local area network controller utilizes an enable bit, a pointer, a counter and an interrupt to create the proper response to a received request with response data frame without the active aid of a host computer.
摘要翻译：具有用于局域网控制器的响应机制和方法的请求利用使能位，指针，计数器和中断来创建对具有响应数据帧的接收到的请求的适当响应，而无需主计算机的主动帮助。

6. 发明授权

US06624681B1 Circuit and method for stopping a clock tree while maintaining PLL lock 有权
标题翻译：在保持PLL锁定的同时停止时钟树的电路和方法
公开(公告)号：US06624681B1
公开(公告)日：2003-09-23
申请号：US09918209
申请日：2001-07-30
申请人： Bruce A. Loyer , Sridhar Subramanian , Michael S. Quimby , Niranjan Venigandla
发明人： Bruce A. Loyer , Sridhar Subramanian , Michael S. Quimby , Niranjan Venigandla
IPC分类号： G06F104
CPC分类号： G06F1/3237 , G06F1/10 , G06F1/3203 , Y02D10/128
摘要： A circuit and method for stopping a clock tree while maintaining PLL lock. A clock circuit includes a locked loop circuit and a clock tree distribution network. The locked loop circuit receives an input clock signal and generates a PLL output clock depending upon a feedback signal. The clock tree is coupled to the locked loop circuit and conveys the PLL output clock to a plurality of clocked circuit elements. The clock circuit further includes a gating circuit and a feedback delay circuit. The gating circuit is coupled between the locked loop circuit the clock tree distribution network and selectively inhibits the PLL output clock from clocking the clock tree distribution network. The feedback delay circuit provides the feedback signal, which represents a delayed version of the PLL output clock, during operation including when the gating circuit inhibits the PLL output clock from clocking the clock tree.
摘要翻译：一种用于在保持PLL锁定的同时停止时钟树的电路和方法。时钟电路包括锁定环路电路和时钟树分配网络。锁定环电路接收输入时钟信号，并根据反馈信号产生PLL输出时钟。时钟树耦合到锁定环电路，并将PLL输出时钟传送到多个时钟电路元件。时钟电路还包括门控电路和反馈延迟电路。门控电路耦合在时钟树分配网络的锁定环路电路之间，并选择性地禁止PLL输出时钟计时时钟树分配网络。反馈延迟电路在操作期间提供反馈信号，其表示PLL输出时钟的延迟版本，包括当门控电路禁止PLL输出时钟计时时钟树时。

7. 发明授权

US06424186B1 Circuit for dynamic signal drive strength compensation 有权
标题翻译：动态信号驱动强度补偿电路
公开(公告)号：US06424186B1
公开(公告)日：2002-07-23
申请号：US09865997
申请日：2001-05-25
申请人： Michael S. Quimby , Bruce A. Loyer
发明人： Michael S. Quimby , Bruce A. Loyer
IPC分类号： H03K300
CPC分类号： H03K19/00384 , H03K19/0005
摘要： A circuit for dynamic signal drive strength compensation. A circuit for compensating the drive strength of an output signal includes an output driver stage including a driver circuit and a drive strength control circuit. The driver circuit may be selectively enabled depending upon a drive strength indicator signal. The driver circuit includes a P-channel transistor which has a P input which is controlled by a P-channel control signal. The driver circuit also includes an N-channel transistor which has an N input which is controlled by an N-channel control signal. The drive strength control circuit may generate the respective P-channel and N-channel control signals. The P-channel control signal is prevented from changing while the P-channel transistor is turned on. The N-channel control signal is prevented from changing while the N-channel transistor is turned on.
摘要翻译：一种用于动态信号驱动强度补偿的电路。用于补偿输出信号的驱动强度的电路包括包括驱动电路和驱动强度控制电路的输出驱动级。可以根据驱动强度指示器信号来选择性地启用驱动器电路。驱动器电路包括P沟道晶体管，其具有由P沟道控制信号控制的P输入。驱动器电路还包括N沟道晶体管，其具有由N沟道控制信号控制的N输入。驱动强度控制电路可以产生相应的P沟道和N沟道控制信号。当P沟道晶体管导通时，防止P沟道控制信号改变。当N沟道晶体管导通时，防止N沟道控制信号改变。

8. 发明授权

US06957413B1 System and method for specifying integrated circuit probe locations 失效
标题翻译：用于指定集成电路探头位置的系统和方法
公开(公告)号：US06957413B1
公开(公告)日：2005-10-18
申请号：US10185288
申请日：2002-06-27
申请人： Tom McKeone , Bruce A. Loyer
发明人： Tom McKeone , Bruce A. Loyer
IPC分类号： G01R31/317 , G01R31/319 , G06F17/50
CPC分类号： G06F17/5068 , G01R31/31722 , G01R31/31723 , G01R31/31905 , G06F17/5022
摘要： A method for including probe locations in an integrated circuit may include specifying probe cells prior to the place and route stage of the design process. The probe cell locations may be specified in a functional description of the integrated circuit, such as an HDL description from which a netlist may be generated. Alternatively, an existing netlist may be edited to include the probe cells on specified nets. The probe locations are included in the physical layout design along with the rest of the integrated circuit components during place and route. The integrated circuit may be fabricated according to the physical layout design so that the fabricated integrated circuit includes the one or more probe locations.
摘要翻译：在集成电路中包括探针位置的方法可以包括在设计过程的放置和布线阶段之前指定探针单元。可以在集成电路的功能描述中指定探针单元位置，诸如可以从其生成网表的HDL描述。或者，可以编辑现有网表以将探针单元包括在指定的网上。探针位置与物理布局设计一起包含在其他集成电路部件的位置和路径中。可以根据物理布局设计制造集成电路，使得制造的集成电路包括一个或多个探针位置。

9. 发明授权

US06889334B1 Multimode system for calibrating a data strobe delay for a memory read operation 有权
标题翻译：用于校准存储器读操作的数据选通延迟的多模系统
公开(公告)号：US06889334B1
公开(公告)日：2005-05-03
申请号：US09969300
申请日：2001-10-02
申请人： James R. Magro , Bruce A. Loyer , Pratik M. Mehta
发明人： James R. Magro , Bruce A. Loyer , Pratik M. Mehta
IPC分类号： G06F1/06 , G11C7/10 , H04L7/00
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1072 , G11C7/222 , G11C2207/2254 , H04L7/0004 , H04L7/0008 , H04L7/0037
摘要： A system for coordinating the timing of a data strobe with data supplied by a memory module to the memory controller read data FIFO of a processor-based system, providing multiple calibration modes. A calibration PDL (programmable delay line) is used to reiteratively test the time taken for a test data strobe to traverse a portion of the memory controller circuit, and to generate a calibration value based upon the time taken. The calibration procedure may be initiated in any one of several modes, including: according to a predetermined schedule; implemented in software; in response to changes in environmental factors such as temperature or voltages sampled at one or more locations; in response to a software-driven trigger; or in response to a user-initiated trigger, communicated to a system of the invention either by input via a user interface to the processor-based system or by a software command.
摘要翻译：用于将数据选通的定时与存储器模块提供的数据协调到存储器控制器的系统，读取基于处理器的系统的数据FIFO，从而提供多种校准模式。校准PDL（可编程延迟线）用于重复测试测试数据选通遍历存储器控制器电路的一部分所花费的时间，并且基于所花费的时间生成校准值。校准过程可以以几种模式中的任何一种启动，包括：根据预定的时间表; 以软件实现响应于在一个或多个位置处采样的环境因素如温度或电压的变化; 响应软件驱动的触发器; 或者响应于用户发起的触发，通过经由用户接口输入到基于处理器的系统或通过软件命令传送到本发明的系统。

10. 发明授权

US06366610B1 Autobauding with adjustment to a programmable baud rate 失效
标题翻译：自动波特率可调整到可编程波特率
公开(公告)号：US06366610B1
公开(公告)日：2002-04-02
申请号：US09080336
申请日：1998-05-15
申请人： Bruce A. Loyer , Melanie D. Typaldos
发明人： Bruce A. Loyer , Melanie D. Typaldos
IPC分类号： H04B1700
CPC分类号： G06F13/385 , H04L25/0262
摘要： An asynchronous receiver/transmitter provides autobauding with adjustment to a programmable baud rate. A baud divisor is calculated based on a detected size of a start bit. The asynchronous receiver/transmitter provides a plurality of baud divisor replacement registers, each register storing a baud divisor threshold and a baud divisor replacement. The baud divisor is compared to the plurality of programmed baud divisor thresholds. Based on the performed hardware comparison, the baud divisor is automatically replaced by a baud divisor replacement for a particular baud divisor range defined by a baud divisor threshold and including the baud divisor. The baud rate corresponding to this baud divisor replacement represents the appropriate baud rate. Autobauding with adjustment to a programmed baud rate corrects for measurement inaccuracies with respect to the start bit size. Autobauding with adjustment to a programmed baud rate also permits an asynchronous receiver/transmitter to reliably support high speed baud rates. Further, the programmable nature of the baud divisor thresholds and baud divisor replacements permits an asynchronous receiver/transmitter to support autubauding at multiple asynchronous receiver/transmitter frequencies.
摘要翻译：异步接收器/发送器通过对可编程波特率进行调整来提供自动波特率。基于检测到的起始位的大小来计算波特除数。异步接收器/发送器提供多个波特除数替换寄存器，每个寄存器存储波特除数阈值和波特除数替换。波特除数与多个编程的波特除数阈值进行比较。根据执行的硬件比较，波特除数由波特除数阈值和波特除数定义的特定波特率除数的波特除数自动替换。对应于该波特率除数的波特率代表相应的波特率。通过调整编程的波特率进行自动波特率校正相对于起始位大小的测量不准确。通过调整编程波特率的自动波特率还允许异步接收器/发送器可靠地支持高速波特率。此外，波特率除数阈值和波特除数替换的可编程性允许异步接收器/发送器在多个异步接收器/发射器频率上支持自动调谐。

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