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1. 发明授权

US07150199B2 Foil strain gage for automated handling and packaging 有权
标题翻译：箔应变计用于自动处理和包装
公开(公告)号：US07150199B2
公开(公告)日：2006-12-19
申请号：US10958545
申请日：2004-10-05
申请人： Thomas Patrick Kieffer , Robert Barry Watson , Sharon Lee Karcher Harris
发明人： Thomas Patrick Kieffer , Robert Barry Watson , Sharon Lee Karcher Harris
IPC分类号： G01F1/00
CPC分类号： G01L1/2287
摘要： An improved strain gage and an improved manufacturing method are disclosed. The strain gage includes a semi-rigid substrate having a thickness of 3 to 30 mils, a resistive strain sensitive foil bonded to the semi-rigid substrate for providing a resistance varying with strain associated with a surface to which the strain gage is attached, a first and a second terminal operatively connected to the resistive strain sensitive foil, and an anti-static layer. The improved strain gage allows for reduced labor content in manufacturing by allowing use of modern automated electronic component manufacturing equipment.
摘要翻译：公开了改进的应变计和改进的制造方法。应变计包括厚度为3至30密耳的半刚性基底，结合到半刚性基底的电阻应变敏感箔，用于提供与应变计附着的表面相关联的应变变化的电阻，第一和第二端子，其可操作地连接到电阻性应变敏感箔片和抗静电层。改进的应变片允许通过允许使用现代自动电子元件制造设备来减少制造中的劳动量。

2. 发明授权

US06477258B1 Transducer assembly 失效
标题翻译：传感器组件
公开(公告)号：US06477258B1
公开(公告)日：2002-11-05
申请号：US09582191
申请日：2000-06-23
申请人： Michael Barry Watson , Richard Herman
发明人： Michael Barry Watson , Richard Herman
IPC分类号： H04R2500
CPC分类号： H04R1/345 , H04B1/385 , H04M1/6041 , H04R1/1016 , H04R1/1075 , H04R1/342 , H04R2201/107
摘要： A transducer assembly for use with an apparatus comprising a sound transmitting earpiece comprises a sound transmitting element (1) adapted to be worn between such an earpiece and the ear, a sound transducer (3), to be located remote from the earpiece and a hollow tube (2) for acoustically coupling the sound transmitting element (1) to the transducer (3).
摘要翻译：一种与包括声音传送耳机的装置一起使用的换能器组件，包括适于佩戴在这种耳机和耳朵之间的声音传播元件（1），位于远离听筒的声音传感器（3）管（2），用于将发声元件（1）声耦合到换能器（3）。

3. 发明授权

US06219758B1 False exception for cancelled delayed requests 失效
标题翻译：取消延迟请求的假异常
公开(公告)号：US06219758B1
公开(公告)日：2001-04-17
申请号：US09047579
申请日：1998-03-25
申请人： Jennifer Almoradie Navarro , Barry Watson Krumm , Chung-Lung Kevin Shum , Pak-kin Mak , Michael Fee
发明人： Jennifer Almoradie Navarro , Barry Watson Krumm , Chung-Lung Kevin Shum , Pak-kin Mak , Michael Fee
IPC分类号： G06F1200
CPC分类号： G06F12/1054
摘要： A central processor uses virtual addresses to access data via cache logic including a DAT and ART, and the cache logic accesses data in the hierarchical storage subsystem using absolute addresses to access data, a part of the first level of the cache memory includes a translator for virtual or real addresses to absolute addresses. When requests are sent for a data fetch and the requested data are not resident in the first level of cache the request for data is delayed and may be forwarded to a lower level of said hierarchical memory, and a delayed request may result in cancellation of any process during a delayed request that has the ability to send back an exception. A delayed request may be rescinded if the central processor has reached an interruptible stage in its pipeline logic at which point, a false exception is forced clearing all I the wait states while the central processor ignores the false exception. Forcing of an exception occurs during dynamic address translation (DAT) or during access register translation (ART). A request for data signal to the storage subsystem cancellation is settable by the first hierarchical level of cache logic. A false exception signal to the first level cache is settable by the storage subsystem logic.
摘要翻译：中央处理器使用虚拟地址通过包括DAT和ART的高速缓存逻辑来访问数据，并且高速缓存逻辑使用绝对地址访问分层存储子系统中的数据来访问数据，高速缓冲存储器的第一级的一部分包括用于虚拟或实际地址到绝对地址。当请求被发送用于数据提取并且所请求的数据不驻留在高速缓存的第一级时，数据请求被延迟并且可以被转发到所述分层存储器的较低级别，并且延迟的请求可能导致任何在具有发回异常的能力的延迟请求过程中。如果中央处理器在其流水线逻辑中达到可中断阶段，则可能会撤销延迟请求，此时在中央处理器忽略错误异常时，强制清除所有I等待状态的错误异常。动态地址转换（DAT）或访问寄存器转换（ART）期间发生异常的强制。对存储子系统取消的数据信号的请求可以由高速缓存逻辑的第一层级设置。存储子系统逻辑可以设置到第一级高速缓存的错误异常信号。

4. 发明授权

US6119219A System serialization with early release of individual processor 失效
标题翻译：系统串行化与早期发布的单个处理器
公开(公告)号：US6119219A
公开(公告)日：2000-09-12
申请号：US70595
申请日：1998-04-30
申请人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
发明人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
IPC分类号： G06F15/177 , G06F9/30 , G06F9/318 , G06F9/38 , G06F9/52 , G06F9/00
CPC分类号： G06F9/3861 , G06F9/3004 , G06F9/30087 , G06F9/30101 , G06F9/3017 , G06F9/3834
摘要： A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e. all processors must pause together), and to allow for CPU retry actions on any of the CPUs in the system at any point in the operation.
摘要翻译：一种用于ESA / 390操作的流水线多处理器系统，其执行硬件控制执行单元中的简单指令集，并且以硬模式设计状态以硬计算执行单元中的简单指令的毫位序列执行复指令集，包括多个CPU处理器，每个CPU处理器都是所述多处理系统的一部分并且能够产生和响应静默请求，并且控制允许ESA / 390系统中的CPU处理IPTE和SSKE的本地缓冲器更新部分的系统操作操作，而不等待所有其他处理器到达可中断点，然后继续执行程序，对操作进行轻微的临时限制，直到IPTE或SSKE操作全局完成。此外，定义了许可内码（LIC）序列，允许这些IPTE和SSKE操作与需要常规系统静止的其他操作（即，所有处理器必须暂停在一起）并存，并允许对任何 CPU在系统中的任何一点操作。

5. 发明授权

US6035392A Computer with optimizing hardware for conditional hedge fetching into cache storage 失效
标题翻译：具有优化硬件的计算机，用于将条件对冲提取到高速缓存存储中
公开(公告)号：US6035392A
公开(公告)日：2000-03-07
申请号：US26923
申请日：1998-02-20
申请人： John Stephen Liptay , Mark Anthony Check , Barry Watson Krumm , Jennifer Almoradie Navarro , Charles Franklin Webb
发明人： John Stephen Liptay , Mark Anthony Check , Barry Watson Krumm , Jennifer Almoradie Navarro , Charles Franklin Webb
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3804
摘要： A computer for executing programs and having a structure for fetching instructions and/or operands along a path which may not be taken by a process being executed by a computer processor having a hierarchical memory structure with data being loaded into cache lines of a cache in the structure, and having block line fetch signal selection logic and computational logic with hedge selection logic for generating line fetch block signals for control of hedging by fetching instructions and/or operands along a path which may not be taken by a process being executed and making selected hedge fetches sensitive to whether the data is in the cache so as to gain the best performance advantage with a selected hedge fetch signal which accompanies each fetch request to the cache to identify whether a line should be loaded if it misses the cache to indicate a selected hedge fetch when this signal is ON, and rejecting a fetch request in the event the selected hedge fetch signal is turned ON if the data is not in the cache, the cache will reject the fetch, and thereafter repeating the fetch request after a fetch request has been rejected when the selected hedge fetch signal was turned ON the data was not in the cache to repeat the fetch request at a later time when it is more certain that the process being executed wants the data, or never repeating the request upon determination that the process being executed does not need the data to he fetched.
摘要翻译：一种用于执行程序并具有用于沿着路径获取指令和/或操作数的结构的计算机，该路径可能不被由具有分层存储器结构的计算机处理器执行的进程执行，其中数据被加载到高速缓存的高速缓存行中结构，并且具有块线取指信号选择逻辑和具有对冲选择逻辑的计算逻辑，用于产生线取指块信号，用于通过沿着路径获取指令和/或操作数来控制对冲，所述路径可能不被被执行的进程采取并且被选择对冲提取对数据是否在高速缓存中敏感，以便通过选择的对冲提取信号获得最佳的性能优势，该信号伴随着每个提取请求到高速缓存，以识别是否应该加载行，如果它错过高速缓存以指示所选择的当该信号为ON时，进行套期提取，并且如果所选择的对冲获取信号为ON，则拒绝提取请求高速缓存不在缓存中，则缓存将拒绝该提取，并且此后在所选择的对冲提取信号被接通时，在拒绝提取请求之后重复该提取请求，该数据不在高速缓存中以在稍后重复该提取请求更确定正在执行的进程想要数据的时间，或者在确定正在执行的进程不需要他获取的数据的情况下，永远不会重复该请求。

6. 发明授权

US5680598A Millicode extended memory addressing using operand access control register to control extended address concatenation 失效
标题翻译： Millicode扩展存储器寻址，使用操作数访问控制寄存器来控制扩展地址级联
公开(公告)号：US5680598A
公开(公告)日：1997-10-21
申请号：US414158
申请日：1995-03-31
申请人： Mark Steven Farrell , Barry Watson Krumm , Jennifer Serena Almoradie Navarro , Charles Franklin Webb
发明人： Mark Steven Farrell , Barry Watson Krumm , Jennifer Serena Almoradie Navarro , Charles Franklin Webb
IPC分类号： G06F9/318 , G06F9/355 , E06F9/34
CPC分类号： G06F9/342 , G06F9/30036 , G06F9/3017
摘要： A millicode instruction loads a millicode address extension register with extended address bits, and an operand access control register that signals when a logical address is to be extended by the extra bits, and when it should be treated as only a 31 bit address.
摘要翻译：一个millicode指令加载一个扩展地址位的millicode地址扩展寄存器和一个操作数访问控制寄存器，用于在逻辑地址扩展一个额外的位时发出信号，当它被当作只有一个31位的地址时。

7. 发明授权

US5649140A System for use in translating virtual addresses into absolute addresses 失效
标题翻译：用于将虚拟地址转换为绝对地址的系统
公开(公告)号：US5649140A
公开(公告)日：1997-07-15
申请号：US414671
申请日：1995-03-31
申请人： Karl Jean Duvalsaint , Mark Steven Farrell , Barry Watson Krumm , Donald William McCauley , Charles Franklin Webb
发明人： Karl Jean Duvalsaint , Mark Steven Farrell , Barry Watson Krumm , Donald William McCauley , Charles Franklin Webb
IPC分类号： G06F12/10 , G06F9/26 , G06F9/34 , G06F12/00 , G06F12/02
CPC分类号： G06F12/109 , G06F12/10
摘要： In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.
摘要翻译：在处理系统中，在虚拟地址和绝对地址之间便于翻译。该系统包括多个寄存器和用第一组地址转换参数加载它们的机制。加法器将平移原点寄存器与偏移寄存器相加以产生基准加偏移值。逻辑电路选择性地组合所选择的寄存器和基本加偏移值以产生有助于确定绝对地址的转换表条目的地址。该确定包括执行前缀，加窗，分区和存储器开始中的一个或多个。从转换起始寄存器到加法器的表示到逻辑电路的转换表项的输出的系统的等待时间最多为一个时钟周期。

8. 外观设计

USD249892S Glucose analyzer 失效
公开(公告)号：USD249892S
公开(公告)日：1978-10-10
申请号：US717777
申请日：1976-08-25
申请人： Robert J. Aul , Philip J. Breno , Wayne J. Zitkus , Barry Watson , Paul R. Maguire
设计人： Robert J. Aul , Philip J. Breno , Wayne J. Zitkus , Barry Watson , Paul R. Maguire

9. 发明授权

US5819078A Addressing extended memory using millicode by concatenating a small millicode address and address extension data 失效
标题翻译：通过连接小的millicode地址和地址扩展数据来寻址使用millicode的扩展内存
公开(公告)号：US5819078A
公开(公告)日：1998-10-06
申请号：US872048
申请日：1997-06-10
申请人： Mark Steven Farrell , Barry Watson Krumm , Jennifer Serena Almoradie Navarro , Charles Franklin Webb
发明人： Mark Steven Farrell , Barry Watson Krumm , Jennifer Serena Almoradie Navarro , Charles Franklin Webb
IPC分类号： G06F9/318 , G06F9/355 , G06F12/06
CPC分类号： G06F9/342 , G06F9/30036 , G06F9/3017
摘要： A millicode instruction loads a millicode address extension register with extended address bits, and an operand access control register that signals when a logical address is to be extended by the extra bits, and when it should be treated as only a 31 bit address.
摘要翻译：一个millicode指令加载一个扩展地址位的millicode地址扩展寄存器和一个操作数访问控制寄存器，用于在逻辑地址扩展一个额外的位时发出信号，当它被当作只有一个31位的地址时。

10. 发明授权

US06079013A Multiprocessor serialization with early release of processors 失效
标题翻译：多处理器串行化与早期版本的处理器
公开(公告)号：US06079013A
公开(公告)日：2000-06-20
申请号：US70429
申请日：1998-04-30
申请人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
发明人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
IPC分类号： G06F9/52 , G06F9/318 , G06F12/06
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/3017
摘要： A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e. all processors must pause together), and to allow for CPU retry actions on any of the CPUs in the system at any point in the operation.
摘要翻译：一种用于ESA / 390操作的流水线多处理器系统，其执行硬件控制执行单元中的简单指令集，并且以硬模式设计状态以硬计算执行单元中的简单指令的毫位序列执行复指令集，包括多个CPU处理器，每个CPU处理器都是所述多处理系统的一部分并且能够产生和响应静默请求，并且控制允许ESA / 390系统中的CPU处理IPTE和SSKE的本地缓冲器更新部分的系统操作操作，而不等待所有其他处理器到达可中断点，然后继续执行程序，对操作进行轻微的临时限制，直到IPTE或SSKE操作全局完成。此外，定义了许可内码（LIC）序列，允许这些IPTE和SSKE操作与需要常规系统静止的其他操作（即，所有处理器必须暂停在一起）并存，并允许对任何 CPU在系统中的任何一点操作。

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