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1. 发明授权

US09909657B2 Continuously variable transmission 有权
公开(公告)号：US09909657B2
公开(公告)日：2018-03-06
申请号：US14400989
申请日：2012-05-22
申请人： Satoshi Uchino , Atsushi Fujikawa
发明人： Satoshi Uchino , Atsushi Fujikawa
IPC分类号： F16H37/02
CPC分类号： F16H37/021 , F16H37/022 , F16H2037/025 , F16H2037/026 , F16H2200/0008
摘要： The driving force from a drive source is transmitted from a main input shaft to a continuously variable transmission mechanism through an input switching mechanism and a first input path in which a first speed-reducing gear is disposed, and is further transmitted to a first output path in which a second speed-reducing gear is disposed, thus establishing a LOW mode. And the driving force is transmitted from the main input shaft to the continuously variable transmission mechanism through the input switching mechanism and a second input path in which a speed-increasing gear, and is further transmitted to a second output path in which a third speed-reducing gear, thus establishing a HI mode. The first speed-reducing gear on the input side, the speed-increasing gear on the input side and the second and third speed-reducing gears on the output side are independent from each other.

2. 发明申请

US20150133257A1 CONTINUOUSLY VARIABLE TRANSMISSION 有权
标题翻译：连续可变传输
公开(公告)号：US20150133257A1
公开(公告)日：2015-05-14
申请号：US14400989
申请日：2012-05-22
申请人： Satoshi Uchino , Atsushi Fujikawa
发明人： Satoshi Uchino , Atsushi Fujikawa
IPC分类号： F16H37/02
CPC分类号： F16H37/021 , F16H37/022 , F16H2037/025 , F16H2037/026 , F16H2200/0008
摘要： The driving force from a drive source is transmitted from a main input shaft to a continuously variable transmission mechanism through an input switching mechanism and a first input path in which a first speed-reducing gear is disposed, and is further transmitted to a first output path in which a second speed-reducing gear is disposed, thus establishing a LOW mode. And the driving force is transmitted from the main input shaft to the continuously variable transmission mechanism through the input switching mechanism and a second input path in which a speed-increasing gear, and is further transmitted to a second output path in which a third speed-reducing gear, thus establishing a HI mode. The_first speed-reducing gear on the input side, the speed-increasing gear on the input side and the second and third speed-reducing gears on the output side are independent from each other.
摘要翻译：来自驱动源的驱动力通过输入切换机构和设置有第一减速齿轮的第一输入路径从主输入轴传递到无级变速传动机构，并且进一步传递到第一输出路径其中设置有第二减速齿轮，从而建立LOW模式。并且驱动力通过输入切换机构从主输入轴传递到无级变速机构，第二输入路径被传递到增速齿轮，并且进一步传递到第二输出路径，在第二输出路径中，减少齿轮，从而建立HI模式。输入侧的第一减速齿轮，输入侧的增速齿轮和输出侧的第二和第三减速齿轮彼此独立。

3. 发明申请

US20080061833A1 Semiconductor device having a pseudo power supply wiring 有权
标题翻译：具有伪电源布线的半导体装置
公开(公告)号：US20080061833A1
公开(公告)日：2008-03-13
申请号：US11892512
申请日：2007-08-23
申请人： Atsushi Fujikawa , Hiromasa Noda
发明人： Atsushi Fujikawa , Hiromasa Noda
IPC分类号： H03K19/0185
CPC分类号： H03K19/0016
摘要： A semiconductor device includes main power supply wirings VDD and VSS, an pseudo power supply wiring VDT, inverters connected between the pseudo power supply wiring VDT and the main power supply wiring VSS, and inverters connected between the main power supply wiring VDD and the main power supply wiring VSS. Between the main power supply wiring VDD and the pseudo power supply wiring VDT, an N-channel MOS transistor and a P-channel MOS transistor that are rendered a conductive state at the time of active are connected in parallel. According to the present invention, the transistors different in conductivity type are used in parallel, and thus, it becomes possible to reduce power consumption at the time of standby while suppressing a decrease in switching speed from a standby state to an active state.
摘要翻译：半导体器件包括主电源布线VDD和VSS，伪电源布线VDT，连接在伪电源布线VDT和主电源布线VSS之间的反相器以及连接在主电源布线VDD和主电源之间的反相器电源接线VSS。在主电源配线VDD和伪电源配线VDT之间并联连接在有源时呈导通状态的N沟道MOS晶体管和P沟道MOS晶体管。根据本发明，并联使用导电型不同的晶体管，因此能够抑制切换速度从待机状态降低到活动状态时的待机时的功耗。

4. 发明授权

US6102176A Hydraulic circuit for transmission 有权
标题翻译：液压回路用于传动
公开(公告)号：US6102176A
公开(公告)日：2000-08-15
申请号：US264237
申请日：1999-03-08
申请人： Atsushi Fujikawa
发明人： Atsushi Fujikawa
IPC分类号： F16H9/00 , F16H61/12 , F16H61/662
CPC分类号： F16H61/12 , F16H2061/122 , F16H2061/1264 , F16H2061/1268 , F16H2061/1292 , F16H61/662 , Y10S477/906
摘要： A hydraulic circuit for a transmission, according to the present invention, comprises a regulator valve (31), a plurality of control valves (34, 35, 45), a restrictor (41), a bypass oil passage (61), a bypass closing valve (42), and a signal pressure generating valve (48). The regulator valve regulates oil discharged from a hydraulic pump driven by a motor to produce line pressure. The plurality of control valves control an operation of the transmission using the line pressure. The control valves include at least one electric control valve. The restrictor is formed on a discharge oil passage which is connected to the regulator valve. The bypass oil passage connects the upstream side and the downstream side of the restrictor while bypassing the restrictor. The bypass closing valve is closable the bypass oil passage by receiving oil pressure produced when the electric control valve breaks down. The signal pressure generating valve generates a signal pressure which corresponds to one of oil pressure on the upstream side of the restrictor and an oil pressure difference between the upstream side and the downstream side when the bypass oil passage is closed. Accordingly, the regulation of line pressure by a regulator valve is not influenced for generating signal pressure corresponding to the speed of the motor and controlling oil pressure when failure occurs.
摘要翻译：根据本发明的用于变速器的液压回路包括调节阀（31），多个控制阀（34,35,45），限流器（41），旁通油通道（61），旁路关闭阀（42）和信号压力生成阀（48）。调节阀调节由电机驱动的液压泵排出的油以产生管路压力。多个控制阀使用管路压力来控制变速器的运转。控制阀包括至少一个电动控制阀。节流器形成在与调节阀连接的排出油路上。旁路油路在绕过限流器的同时连接限流器的上游侧和下游侧。旁路关闭阀通过接收电控阀故障时产生的油压而关闭旁通油路。信号压力产生阀产生对应于节流器上游侧的油压之一的信号压力和旁通油路关闭时的上游侧和下游侧的油压差。因此，通过调节阀对管路压力的调节对于产生与电动机的速度相对应的信号压力并且在故障发生时控制油压不受影响。

5. 发明申请

US20100090675A1 Semiconductor device and test method therefor 有权
标题翻译：半导体器件及其测试方法
公开(公告)号：US20100090675A1
公开(公告)日：2010-04-15
申请号：US12292432
申请日：2008-11-19
申请人： Chiaki Dono , Atsushi Fujikawa
发明人： Chiaki Dono , Atsushi Fujikawa
IPC分类号： G05F3/16 , G01R31/00
CPC分类号： G01R31/31723 , G11C29/02 , G11C29/021 , G11C29/1201 , G11C29/48
摘要： Disclosed is a semiconductor device including internal power supply generating circuits for generating internal power supplies and data terminals via which data signals are output or input/output. The internal power supply monitor terminals are in common use with the data terminals. The semiconductor device also includes selection circuits for selecting, by a test control signal, whether or not output voltages of the internal power supply generating circuits are to be output to the data terminals.
摘要翻译：公开了一种半导体器件，包括用于产生内部电源的内部电源产生电路和数据信号被输出或输出的数据端子。内部电源监视器端子与数据终端通用。半导体器件还包括选择电路，用于通过测试控制信号选择内部电源发生电路的输出电压是否被输出到数据终端。

6. 发明授权

US07532036B2 Semiconductor device having a pseudo power supply wiring 有权
标题翻译：具有伪电源布线的半导体装置
公开(公告)号：US07532036B2
公开(公告)日：2009-05-12
申请号：US11892512
申请日：2007-08-23
申请人： Atsushi Fujikawa , Hiromasa Noda
发明人： Atsushi Fujikawa , Hiromasa Noda
IPC分类号： H03K19/096 , H03K19/003
CPC分类号： H03K19/0016
摘要： A semiconductor device includes main power supply wirings VDD and VSS, an pseudo power supply wiring VDT, inverters connected between the pseudo power supply wiring VDT and the main power supply wiring VSS, and inverters connected between the main power supply wiring VDD and the main power supply wiring VSS. Between the main power supply wiring VDD and the pseudo power supply wiring VDT, an N-channel MOS transistor and a P-channel MOS transistor that are rendered a conductive state at the time of active are connected in parallel. According to the present invention, the transistors different in conductivity type are used in parallel, and thus, it becomes possible to reduce power consumption at the time of standby while suppressing a decrease in switching speed from a standby state to an active state.
摘要翻译：半导体器件包括主电源布线VDD和VSS，伪电源布线VDT，连接在伪电源布线VDT和主电源布线VSS之间的反相器以及连接在主电源布线VDD和主电源之间的反相器电源接线VSS。在主电源配线VDD和伪电源配线VDT之间并联连接在有源时呈导通状态的N沟道MOS晶体管和P沟道MOS晶体管。根据本发明，并联使用导电型不同的晶体管，因此能够抑制切换速度从待机状态降低到活动状态时的待机时的功耗。

7. 发明授权

US06655232B2 Hydraulic controller for transmission 失效
公开(公告)号：US06655232B2
公开(公告)日：2003-12-02
申请号：US10125387
申请日：2002-04-19
申请人： Atsushi Fujikawa , Shuji Ichijo , Yukihiko Fukushima , Makoto Sumi , Mitsuro Ohtaki , Katsuyuki Narai , Takashi Hasegawa , Shuichi Fujimoto
发明人： Atsushi Fujikawa , Shuji Ichijo , Yukihiko Fukushima , Makoto Sumi , Mitsuro Ohtaki , Katsuyuki Narai , Takashi Hasegawa , Shuichi Fujimoto
IPC分类号： F16H5900
CPC分类号： F16H61/0025 , F16H61/0009 , F16H61/0021 , F16H61/662 , Y10T74/2186
摘要： A hydraulic controller comprises a first hydraulic control valve 60, which is mounted on an end face S1 of a first housing unit H1, an oil pump 50, which is mounted on the first hydraulic control valve 60, and an input shaft 1 of a transmission, which shaft is provided rotatably in a transmission housing. The oil pump 50 comprises an outer rotor 52 and an inner rotor 53 in a pump casing 51 and 54, which is mounted on the valve body of the first hydraulic control valve 60. The input shaft 1, which is inserted into the pump casing and fit into the inner rotor 53, rotates and drives the inner rotor. The oil pump 50 sucks oil from the bottom of the transmission housing and supplies it through the mounted part into the first hydraulic control valve 60.

8. 发明申请

US20150270268A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20150270268A1
公开(公告)日：2015-09-24
申请号：US14440964
申请日：2013-10-21
申请人： Atsushi Fujikawa
发明人： Atsushi Fujikawa
IPC分类号： H01L27/092 , H01L29/10 , H01L29/06 , H01L29/78 , H01L29/417
CPC分类号： H01L27/0922 , H01L21/823437 , H01L21/823487 , H01L21/823828 , H01L21/823885 , H01L27/092 , H01L29/0653 , H01L29/1037 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/66666 , H01L29/7827
摘要： The present invention is provided with: a plurality of pillars vertically arranged on a semiconductor substrate; a plurality of second diffusion layers respectively arranged on the upper part of each pillar; a conductive layer electrically connected to at least one of the second diffusion layers; and at least one contact formed on at least one of the plurality of second diffusion layers, the number of electrical connections (contacts) between the second diffusion layers and the conductive layer being smaller than the number of pillars, and the number of connections between the pillars and the conductive layer being changeable as needed.
摘要翻译：本发明提供：垂直设置在半导体衬底上的多个柱; 分别设置在每个支柱的上部的多个第二扩散层; 电连接到所述第二扩散层中的至少一个的导电层; 以及形成在所述多个第二扩散层中的至少一个上的至少一个触点，所述第二扩散层和所述导电层之间的电连接数（触点数）小于所述支柱的数量，以及所述第二扩散层之间的连接数支柱和导电层根据需要是可变的。

9. 发明授权

US08116156B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08116156B2
公开(公告)日：2012-02-14
申请号：US12320891
申请日：2009-02-06
申请人： Yoshiro Riho , Atsushi Fujikawa
发明人： Yoshiro Riho , Atsushi Fujikawa
IPC分类号： G11C29/00
CPC分类号： G11C8/10 , G11C29/84
摘要： There are provided a row predecoder that predocodes an address irrespective of whether the address to which access is requested is a defective address, a row main decoder that controls a sub-word driver, based on a predecode signal generated by the row predecoder, and a repair determining circuit that determines whether the address is a defective address. The row main decoder, the row predecoder, and the repair determining circuit all have a shape in which a column direction is set to be a longitudinal direction. The row predecoder and the repair determining circuit are arranged adjacent to each other in the column direction, and are arranged in parallel with the row main decoder.
摘要翻译：提供了一种行预解码器，其对地址进行预编码，而不管请求访问的地址是否是缺陷地址，基于由行预解码器生成的预解码信号来控制子字驱动器的行主解码器，以及修复确定电路，确定地址是否是有缺陷的地址。行主解码器，行预解码器和修复确定电路都具有列方向被设置为纵向的形状。行预解码器和修复确定电路在列方向上彼此相邻布置，并且与行主解码器并行布置。

10. 发明授权

US07898884B2 Semiconductor device and test method therefor 有权
标题翻译：半导体器件及其测试方法
公开(公告)号：US07898884B2
公开(公告)日：2011-03-01
申请号：US12292432
申请日：2008-11-19
申请人： Chiaki Dono , Atsushi Fujikawa
发明人： Chiaki Dono , Atsushi Fujikawa
IPC分类号： G11C7/00
CPC分类号： G01R31/31723 , G11C29/02 , G11C29/021 , G11C29/1201 , G11C29/48
摘要： Disclosed is a semiconductor device including internal power supply generating circuits for generating internal power supplies and data terminals via which data signals are output or input/output. The internal power supply monitor terminals are in common use with the data terminals. The semiconductor device also includes selection circuits for selecting, by a test control signal, whether or not output voltages of the internal power supply generating circuits are to be output to the data terminals.
摘要翻译：公开了一种半导体器件，包括用于产生内部电源的内部电源产生电路和数据信号被输出或输出的数据端子。内部电源监视器端子与数据终端通用。半导体器件还包括选择电路，用于通过测试控制信号选择内部电源发生电路的输出电压是否被输出到数据终端。

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