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1. 发明授权

US08669794B2 Circuit for detecting a voltage change using a time-to-digital converter 有权
标题翻译：用于使用时间 - 数字转换器检测电压变化的电路
公开(公告)号：US08669794B2
公开(公告)日：2014-03-11
申请号：US13401296
申请日：2012-02-21
申请人： Sang Wook Park , Ashwin Raghunathan , Marzio Pedrali-Noy
发明人： Sang Wook Park , Ashwin Raghunathan , Marzio Pedrali-Noy
IPC分类号： H03L7/06
CPC分类号： G01R19/255 , G04F10/005
摘要： A circuit for detecting a voltage change is described. The circuit includes a supply insensitive pulse generator that generates a pulse signal. The circuit also includes a time-to-digital converter coupled to the supply insensitive pulse generator. The time-to-digital converter generates a digital signal based on the pulse signal and a voltage. The circuit also includes a controller coupled to the time-to-digital converter that detects a voltage change based on the digital signal.
摘要翻译：描述用于检测电压变化的电路。电路包括产生脉冲信号的电源不敏感脉冲发生器。电路还包括耦合到不敏感脉冲发生器的时间 - 数字转换器。时间 - 数字转换器基于脉冲信号和电压产生数字信号。电路还包括耦合到时间 - 数字转换器的控制器，其基于数字信号来检测电压变化。

2. 发明授权

US07880554B2 Periodic timing jitter reduction in oscillatory systems 有权
标题翻译：振荡系统周期性定时抖动减少
公开(公告)号：US07880554B2
公开(公告)日：2011-02-01
申请号：US12432515
申请日：2009-04-29
申请人： Ashwin Raghunathan , Marzio Pedrali-Noy
发明人： Ashwin Raghunathan , Marzio Pedrali-Noy
IPC分类号： H03L1/00 , G05F1/10
CPC分类号： H03L7/08 , H03K3/013
摘要： A device including a voltage regulator with an adaptive switching frequency circuit for noise-sensitive analog circuits, such as oscillatory systems with phase-lock loops (PLLs) and voltage-controlled oscillators (VCOs) is described. In an exemplary embodiment, the device includes a reference clock oscillator, a low-jitter oscillator, a power supply including a clock signal input to regulate a power supply voltage for the low-jitter oscillator, a clock detector to generate a clock detector control signal when the low-jitter oscillator output frequency is stable, and a multiplexer to select between a reference clock oscillator output signal and a low-jitter oscillator output signal as the clock signal input to the power supply to mitigate effects of period jitter in the low-jitter oscillator output signal when the clock detector control signal is asserted. In a further exemplary embodiment, a clock detector control signal is configured to control the multiplexer to select the low-jitter oscillator output signal as the clock signal input to the power supply when the low-jitter oscillator output frequency is stable.
摘要翻译：描述了包括具有用于噪声敏感模拟电路的自适应开关频率电路的电压调节器的装置，例如具有锁相环（PLL）和压控振荡器（VCO）的振荡系统。在示例性实施例中，该器件包括参考时钟振荡器，低抖动振荡器，包括用于调节低抖动振荡器的电源电压的时钟信号输入的电源;产生时钟检测器控制信号的时钟检测器当低抖动振荡器输出频率稳定时，以及多路复用器在参考时钟振荡器输出信号和低抖动振荡器输出信号之间选择时钟信号输入到电源，以减轻低电平时钟周期抖动的影响，当时钟检测器控制信号被置位时，抖动振荡器输出信号。在另一示例性实施例中，时钟检测器控制信号被配置为当低抖动振荡器输出频率稳定时，控制多路复用器选择低抖动振荡器输出信号作为输入到电源的时钟信号。

3. 发明授权

US08362848B2 Supply-regulated VCO architecture 有权
标题翻译：电源调节VCO架构
公开(公告)号：US08362848B2
公开(公告)日：2013-01-29
申请号：US13082313
申请日：2011-04-07
申请人： Ashwin Raghunathan , Marzio Pedrali-Noy , Sameer Wadhwa
发明人： Ashwin Raghunathan , Marzio Pedrali-Noy , Sameer Wadhwa
IPC分类号： H03L1/00 , H03L7/099 , H03K3/03
CPC分类号： H03L7/0995 , H03L7/0805 , H03L7/099 , H03L7/24
摘要： A supply-regulated VCO exhibits reduced or no supply sensitivity peaking. The VCO includes an oscillator whose supply current is regulated to control the oscillating frequency of the oscillator. A VCO input signal controls the supply current so that there is a relationship between the input signal and the oscillator output frequency. Power supply noise that might otherwise affect oscillator operation is shunted from a supply current input lead of the oscillator to ground by a bypass capacitor. In one example, an auxiliary circuit supplies an auxiliary supply current to the oscillator, thereby reducing the amount of supply current a supply regulation control loop circuit must supply. In another example, a supply regulation control loop circuit supplies a control current to a main oscillator, but the bypass capacitor is not coupled to this oscillator but rather is coupled to a slave oscillator that is injection locked to the main oscillator.
摘要翻译：供应调节的VCO表现出减少或没有供应灵敏度峰值。 VCO包括一个振荡器，其供电电流被调节以控制振荡器的振荡频率。 VCO输入信号控制电源电流，使得输入信号和振荡器输出频率之间存在关系。否则可能会影响振荡器运行的电源噪声从旁路电容器的振荡器的电源电流输入引脚分流到地。在一个示例中，辅助电路向振荡器提供辅助电源电流，从而减少供电调节控制回路电路必须供应的供电电流量。在另一示例中，电源调节控制回路电路向主振荡器提供控制电流，但是旁路电容器不耦合到该振荡器，而是耦合到被注入锁定到主振荡器的从属振荡器。

4. 发明申请

US20120256693A1 SUPPLY-REGULATED VCO ARCHITECTURE 有权
标题翻译：供应调节的VCO架构
公开(公告)号：US20120256693A1
公开(公告)日：2012-10-11
申请号：US13082313
申请日：2011-04-07
申请人： Ashwin Raghunathan , Marzio Pedrali-Noy , Sameer Wadhwa
发明人： Ashwin Raghunathan , Marzio Pedrali-Noy , Sameer Wadhwa
IPC分类号： H03L7/06
CPC分类号： H03L7/0995 , H03L7/0805 , H03L7/099 , H03L7/24
摘要： A supply-regulated VCO exhibits reduced or no supply sensitivity peaking. The VCO includes an oscillator whose supply current is regulated to control the oscillating frequency of the oscillator. A VCO input signal controls the supply current so that there is a relationship between the input signal and the oscillator output frequency. Power supply noise that might otherwise affect oscillator operation is shunted from a supply current input lead of the oscillator to ground by a bypass capacitor. In one example, an auxiliary circuit supplies an auxiliary supply current to the oscillator, thereby reducing the amount of supply current a supply regulation control loop circuit must supply. In another example, a supply regulation control loop circuit supplies a control current to a main oscillator, but the bypass capacitor is not coupled to this oscillator but rather is coupled to a slave oscillator that is injection locked to the main oscillator.
摘要翻译：供应调节的VCO表现出减少或没有供应灵敏度峰值。 VCO包括一个振荡器，其供电电流被调节以控制振荡器的振荡频率。 VCO输入信号控制电源电流，使得输入信号和振荡器输出频率之间存在关系。否则可能会影响振荡器运行的电源噪声从旁路电容器的振荡器的电源电流输入引脚分流到地。在一个示例中，辅助电路向振荡器提供辅助电源电流，从而减少供电调节控制回路电路必须供应的供电电流量。在另一示例中，电源调节控制回路电路向主振荡器提供控制电流，但是旁路电容器不耦合到该振荡器，而是耦合到被注入锁定到主振荡器的从属振荡器。

5. 发明申请

US20110211404A1 Recalibration Systems and Techniques for Electronic Memory Applications 有权
标题翻译：电子内存应用的重新校准系统和技术
公开(公告)号：US20110211404A1
公开(公告)日：2011-09-01
申请号：US12714767
申请日：2010-03-01
申请人： Ashwin Raghunathan , Marzio Pedrali-Noy
发明人： Ashwin Raghunathan , Marzio Pedrali-Noy
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C7/04 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： A memory circuit includes a delay module receiving a strobe signal and producing a delayed strobe signal therefrom. The memory circuit also includes a calibration module that initiates recalibration of the delay module when the calibration module discerns that the delayed strobe signal is within a predetermined proximity of an edge of a reference signal. The memory circuit can be included in a memory interface. Furthermore, in some embodiments, a strobe signal can be used as the reference signal.
摘要翻译：存储电路包括延迟模块，其接收选通信号并产生延迟的选通信号。存储器电路还包括校准模块，当校准模块识别延迟的选通信号在参考信号的边缘的预定接近度内时，启动对延迟模块的重新校准。存储器电路可以包括在存储器接口中。此外，在一些实施例中，可以使用选通信号作为参考信号。

6. 发明授权

US07973612B2 Supply-regulated phase-locked loop (PLL) and method of using 有权
标题翻译：供电调节锁相环（PLL）及其使用方法
公开(公告)号：US07973612B2
公开(公告)日：2011-07-05
申请号：US12430104
申请日：2009-04-26
申请人： Ashwin Raghunathan , Marzio Pedrali-Noy
发明人： Ashwin Raghunathan , Marzio Pedrali-Noy
IPC分类号： H03L7/099
CPC分类号： H03L7/099 , H03L7/22
摘要： A supply-regulated Phase-locked loop (PLL) is provided. The PLL comprises a supply-regulating loop, a voltage-controlled oscillator (VCO), and a programmable decoupling capacitor array for the VCO. The capacitance of the VCO decoupling capacitor array is adjustable to be equal to N times CUNIT, where N is the current value of a multiplication factor of a divide-by-N circuit and CUNIT is a unit capacitance characterized for a processing technology chosen for fabricating the decoupling capacitor array. When the PLL switches from one frequency band to another, a higher-order pole introduced by the VCO decoupling capacitor tracks the PLL reference frequency, thus improving the PLL operational stability.
摘要翻译：提供电源调节锁相环（PLL）。 PLL包括电源调节回路，压控振荡器（VCO）和用于VCO的可编程去耦电容器阵列。 VCO去耦电容阵列的电容可以调整为N次CUNIT，其中N是N分频电路的乘法因子的电流值，CUNIT是一种单位电容，其特征在于用于制造的处理技术去耦电容阵列。当PLL从一个频带切换到另一个频带时，VCO去耦电容引入的高阶极跟踪PLL参考频率，从而提高PLL的运行稳定性。

7. 发明授权

US07932757B2 Techniques for minimizing control voltage ripple due to charge pump leakage in phase locked loop circuits 有权
标题翻译：在锁相环电路中由于电荷泵泄漏而使控制电压纹波最小化的技术
公开(公告)号：US07932757B2
公开(公告)日：2011-04-26
申请号：US12367969
申请日：2009-02-09
申请人： Ashwin Raghunathan , Marzio Pedrali-Noy
发明人： Ashwin Raghunathan , Marzio Pedrali-Noy
IPC分类号： H03L7/06
CPC分类号： H03L7/0891 , H03L7/18
摘要： Techniques for adaptively control of a loop filter sampling interval to mitigate the effects of charge pump leakage current in an apparatus including a phase lock loop circuit are provided. In one aspect, the apparatus includes a voltage controlled oscillator (VCO), a phase frequency detector (PFD) providing a phase comparison operation, a loop filter providing a control voltage to lock the VCO to a desired operating frequency, and a charge pump configured to provide an output signal to the loop filter in response to at least one of an UP pulse and a DOWN pulse. The apparatus further includes a sampling switch, coupled between an input of the loop filter, an output of the charge pump, and characterized by a sampling interval. A sampling switch controller is configured to adaptively control the width of the sampling interval in order to mitigate the effects of leakage current from the charge pump by closing the sampling switch in advance of the phase comparison operation and opening the sampling switch when the phase comparison operation is completed.
摘要翻译：提供了用于自适应地控制环路滤波器采样间隔以减轻包括锁相环电路的装置中的电荷泵漏电流的影响的技术。一方面，该装置包括压控振荡器（VCO），提供相位比较操作的相位频率检测器（PFD），提供控制电压以将VCO锁定到所需工作频率的环路滤波器，以及配置以响应于UP脉冲和DOWN脉冲中的至少一个向环路滤波器提供输出信号。该装置还包括一个采样开关，耦合在环路滤波器的输入端，电荷泵的输出端之间，并以采样间隔为特征。采样开关控制器被配置为自适应地控制采样间隔的宽度，以便通过在相位比较操作之前闭合采样开关来减轻来自电荷泵的泄漏电流的影响，并且当相位比较操作完成了。

8. 发明申请

US20110063929A1 DELAY LINE THAT TRACKS SETUP TIME OF A LATCHING ELEMENT OVER PVT 有权
标题翻译：延迟线，跟踪PVT上的锁定元件的设置时间
公开(公告)号：US20110063929A1
公开(公告)日：2011-03-17
申请号：US12559585
申请日：2009-09-15
申请人： Ashwin Raghunathan , Marzio Pedrali Noy
发明人： Ashwin Raghunathan , Marzio Pedrali Noy
IPC分类号： G11C7/22 , G11C7/00
CPC分类号： H03K3/0375 , H03K3/356156
摘要： A latching element latches incoming data into an integrated circuit. The latching element (for example, a latch or flip-flop) can be considered to include a data path portion, a clock path portion, and an ideal latching element. In one embodiment, an open-loop replica of the data path portion is disposed in a clock signal path between a clock input terminal of the integrated circuit and a clock input lead of the latching element. In a second embodiment, an additional replica of the clock path portion is disposed in a data signal path between a data terminal of the integrated circuit and a data input lead of the latching element. The replica circuits help prevent changes in skew between a data path propagation time to the ideal latching element and clock path propagation time to the ideal latching element. Setup times remain substantially constant over PVT (process, supply voltage, temperature).
摘要翻译：锁存元件将输入数据锁存到集成电路中。锁存元件（例如，锁存器或触发器）可以被认为包括数据路径部分，时钟路径部分和理想的锁存元件。在一个实施例中，数据路径部分的开环副本被布置在集成电路的时钟输入端和锁存元件的时钟输入引线之间的时钟信号路径中。在第二实施例中，时钟路径部分的附加副本被布置在集成电路的数据端和锁存元件的数据输入引线之间的数据信号路径中。复制电路有助于防止在理想锁存元件的数据路径传播时间与理想锁存元件的时钟路径传播时间之间的偏差变化。 PVT（工艺，电源电压，温度）的设置时间基本保持不变。

9. 发明申请

US20100194471A1 PERIODIC TIMING JIPERIODIC TIMING JITTER REDUCTION IN OSCILLATORY SYSTEMS 有权
标题翻译：振荡系统中的定时定时时序抖动减少
公开(公告)号：US20100194471A1
公开(公告)日：2010-08-05
申请号：US12432515
申请日：2009-04-29
申请人： Ashwin Raghunathan , Marzio Pedrali-Noy
发明人： Ashwin Raghunathan , Marzio Pedrali-Noy
IPC分类号： H03B25/00 , G06F1/04
CPC分类号： H03L7/08 , H03K3/013
摘要： A device including a voltage regulator with an adaptive switching frequency circuit for noise-sensitive analog circuits, such as oscillatory systems with phase-lock loops (PLLs) and voltage-controlled oscillators (VCOs) is described. In an exemplary embodiment, the device includes a reference clock oscillator, a low-jitter oscillator, a power supply including a clock signal input to regulate a power supply voltage for the low-jitter oscillator, a clock detector to generate a clock detector control signal when the low-jitter oscillator output frequency is stable, and a multiplexer to select between a reference clock oscillator output signal and a low-jitter oscillator output signal as the clock signal input to the power supply to mitigate effects of period jitter in the low-jitter oscillator output signal when the clock detector control signal is asserted. In a further exemplary embodiment, a clock detector control signal is configured to control the multiplexer to select the low-jitter oscillator output signal as the clock signal input to the power supply when the low-jitter oscillator output frequency is stable.
摘要翻译：描述了包括具有用于噪声敏感模拟电路的自适应开关频率电路的电压调节器的装置，例如具有锁相环（PLL）和压控振荡器（VCO）的振荡系统。在示例性实施例中，该器件包括参考时钟振荡器，低抖动振荡器，包括用于调节低抖动振荡器的电源电压的时钟信号输入的电源;产生时钟检测器控制信号的时钟检测器当低抖动振荡器输出频率稳定时，以及多路复用器在参考时钟振荡器输出信号和低抖动振荡器输出信号之间选择时钟信号输入到电源，以减轻低电平时钟周期抖动的影响，当时钟检测器控制信号被置位时，抖动振荡器输出信号。在另一示例性实施例中，时钟检测器控制信号被配置为当低抖动振荡器输出频率稳定时，控制多路复用器选择低抖动振荡器输出信号作为输入到电源的时钟信号。

10. 发明申请

US20100117701A1 TECHNIQUES FOR MINIMIZING CONTROL VOLTAGE NOISE DUE TO CHARGE PUMP LEAKAGE IN PHASE LOCKED LOOP CIRCUITS 失效
标题翻译：用于最小化相位锁定环路中充电泵泄漏的控制电压噪声的技术
公开(公告)号：US20100117701A1
公开(公告)日：2010-05-13
申请号：US12367980
申请日：2009-02-09
申请人： Ashwin Raghunathan , Marzio Pedrali-Noy
发明人： Ashwin Raghunathan , Marzio Pedrali-Noy
IPC分类号： H03K3/017
CPC分类号： H03L7/0891 , H03L7/18
摘要： Techniques for adaptively control of a loop filter sampling interval to mitigate the effects of charge pump output noise in an apparatus including a phase lock loop circuit are provided. In one aspect, the apparatus includes a voltage controlled oscillator (VCO), a phase frequency detector (PFD) providing a phase comparison operation, a loop filter providing a control voltage to lock the VCO to a desired operating frequency, and a charge pump configured to provide an output signal to the loop filter in response to at least one of an UP pulse and a DOWN pulse. The apparatus further includes a sampling switch, coupled between an input of the loop filter, an output of the charge pump, and characterized by a sampling interval. A sampling switch controller is configured to adaptively control the width of the sampling interval in order to mitigate the effects of output noise from the charge pump by closing the sampling switch in advance of the phase comparison operation and opening the sampling switch when the phase comparison operation is completed.
摘要翻译：提供了用于自适应地控制环路滤波器采样间隔以减轻包括锁相环电路的装置中的电荷泵输出噪声的影响的技术。一方面，该装置包括压控振荡器（VCO），提供相位比较操作的相位频率检测器（PFD），提供控制电压以将VCO锁定到所需工作频率的环路滤波器，以及配置以响应于UP脉冲和DOWN脉冲中的至少一个向环路滤波器提供输出信号。该装置还包括一个采样开关，耦合在环路滤波器的输入端，电荷泵的输出端之间，并以采样间隔为特征。采样开关控制器被配置为自适应地控制采样间隔的宽度，以便通过在相位比较操作之前关闭采样开关来减轻来自电荷泵的输出噪声的影响，并且当相位比较操作完成了。

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