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1. 发明申请

US20120151185A1 FINE-GRAINED PRIVILEGE ESCALATION 失效
标题翻译：精细化的特权自治
公开(公告)号：US20120151185A1
公开(公告)日：2012-06-14
申请号：US12967085
申请日：2010-12-14
申请人： Anthony J. Bybell , Anup Wadia
发明人： Anthony J. Bybell , Anup Wadia
IPC分类号： G06F9/318 , G06F9/312 , G06F9/305
CPC分类号： G06F9/30189 , G06F9/30076 , G06F9/3802 , G06F9/382
摘要： A processor and a method for privilege escalation in a processor are provided. The method may comprise fetching an instruction from a fetch address, where the instruction requires the processor to be in supervisor mode for execution, and determining whether the fetch address is within a predetermined address range. The instruction is filtered through an instruction mask and then it is determined whether the instruction, after being filtered through the mask, equals the value in an instruction value compare register. The processor privilege is raised to supervisor mode for execution of the instruction in response to the fetch address being within the predetermined address range and the filtered instruction equaling the value in the instruction value compare register, wherein the processor privilege is raised to supervisor mode without use of an interrupt. The processor privilege returns to its previous level after execution of the instruction.
摘要翻译：提供了一种用于处理器中的特权升级的处理器和方法。该方法可以包括从获取地址获取指令，其中指令要求处理器处于监控模式以执行，以及确定获取地址是否在预定地址范围内。指令通过指令屏蔽过滤，然后确定在通过掩码滤波后的指令是否等于指令值比较寄存器中的值。处理器特权被提升到管理员模式，以响应于提取地址在预定地址范围内执行指令，并且滤波指令等于指令值比较寄存器中的值，其中处理器特权被提升到管理员模式而不使用的中断。执行指令后，处理器权限返回到上一级。

2. 发明授权

US07467366B2 Method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between components 失效
标题翻译：用于生成用于识别耦合在组件之间的硬件设备中的关键定时路径的定时路径软件监视器的方法
公开(公告)号：US07467366B2
公开(公告)日：2008-12-16
申请号：US11535203
申请日：2006-09-26
申请人： John B. Blankenship , Kevin N. Magill , Jeffrey R. Summers , Anup Wadia
发明人： John B. Blankenship , Kevin N. Magill , Jeffrey R. Summers , Anup Wadia
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5031
摘要： A method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between first and second components is provided. The method includes generating a static timing report associated with the hardware devices. The static timing report has names of the hardware devices and wire names associated with wires coupled to the hardware devices. The method further includes automatically generating the timing path software monitor based on the static timing report that monitors binary values associated with the wire names at a first clock cycle and a transition of binary values associated with the wire names during a second clock cycle after the first clock cycle. The timing path software monitor indicates a critical timing path is identified when the transition of one of the binary values received by the second component occurs during the second clock cycle.
摘要翻译：提供了一种用于生成用于识别耦合在第一和第二组件之间的硬件设备中的关键定时路径的定时路径软件监视器的方法。该方法包括生成与硬件设备相关联的静态定时报告。静态定时报告具有与耦合到硬件设备的线路相关联的硬件设备和线名称。该方法还包括基于静态定时报告自动生成定时路径软件监视器，静态定时报告在第一时钟周期监视与线名称相关联的二进制值，以及在第一时钟周期之后的第二时钟周期期间与线名相关联的二进制值的转变时钟周期。定时路径软件监视器指示当在第二时钟周期期间发生由第二分量接收的二进制值之一的转换时，识别关键定时路径。

3. 发明申请

US20080077895A1 METHOD FOR GENERATING A TIMING PATH SOFTWARE MONITOR FOR IDENTIFYING A CRITICAL TIMING PATH IN HARDWARE DEVICES COUPLED BETWEEN COMPONENTS 失效
标题翻译：用于识别在组件之间耦合的硬件设备中的关键时序路径的定时路径软件监视器的方法
公开(公告)号：US20080077895A1
公开(公告)日：2008-03-27
申请号：US11535203
申请日：2006-09-26
申请人： John B. Blankenship , Kevin N. Magill , Jeffrey R. Summers , Anup Wadia
发明人： John B. Blankenship , Kevin N. Magill , Jeffrey R. Summers , Anup Wadia
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5031
摘要： A method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between first and second components is provided. The method includes generating a static timing report associated with the hardware devices. The static timing report has names of the hardware devices and wire names associated with wires coupled to the hardware devices. The method further includes automatically generating the timing path software monitor based on the static timing report that monitors binary values associated with the wire names at a first clock cycle and a transition of binary values associated with the wire names during a second clock cycle after the first clock cycle. The timing path software monitor indicates a critical timing path is identified when the transition of one of the binary values received by the second component occurs during the second clock cycle.
摘要翻译：提供了一种用于生成用于识别耦合在第一和第二组件之间的硬件设备中的关键定时路径的定时路径软件监视器的方法。该方法包括生成与硬件设备相关联的静态定时报告。静态定时报告具有与耦合到硬件设备的线路相关联的硬件设备和线名称。该方法还包括基于静态定时报告自动生成定时路径软件监视器，静态定时报告在第一时钟周期监视与线名称相关联的二进制值，以及在第一时钟周期之后的第二时钟周期期间与线名相关联的二进制值的转变时钟周期。定时路径软件监视器指示当在第二时钟周期期间发生由第二分量接收的二进制值之一的转换时，识别关键定时路径。

4. 发明授权

US08782380B2 Fine-grained privilege escalation 失效
标题翻译：细粒度特权升级
公开(公告)号：US08782380B2
公开(公告)日：2014-07-15
申请号：US12967085
申请日：2010-12-14
申请人： Anthony J. Bybell , Anup Wadia
发明人： Anthony J. Bybell , Anup Wadia
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/30076 , G06F9/3802 , G06F9/382
摘要： A processor and a method for privilege escalation in a processor are provided. The method may comprise fetching an instruction from a fetch address, where the instruction requires the processor to be in supervisor mode for execution, and determining whether the fetch address is within a predetermined address range. The instruction is filtered through an instruction mask and then it is determined whether the instruction, after being filtered through the mask, equals the value in an instruction value compare register. The processor privilege is raised to supervisor mode for execution of the instruction in response to the fetch address being within the predetermined address range and the filtered instruction equaling the value in the instruction value compare register, wherein the processor privilege is raised to supervisor mode without use of an interrupt. The processor privilege returns to its previous level after execution of the instruction.
摘要翻译：提供了一种用于处理器中的特权升级的处理器和方法。该方法可以包括从获取地址获取指令，其中指令要求处理器处于监控模式以执行，以及确定获取地址是否在预定地址范围内。指令通过指令屏蔽过滤，然后确定在通过掩码滤波后的指令是否等于指令值比较寄存器中的值。处理器特权被提升到管理员模式，以响应于提取地址在预定地址范围内执行指令，并且滤波指令等于指令值比较寄存器中的值，其中处理器特权被提升到管理员模式而不使用的中断。执行指令后，处理器权限返回到上一级。

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