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1. 发明申请

US20120153990A1 EMBEDDED BLOCK CONFIGURATION VIA SHIFTING 审中-公开
标题翻译：嵌入式块配置通过移位
公开(公告)号：US20120153990A1
公开(公告)日：2012-06-21
申请号：US12971435
申请日：2010-12-17
申请人： ANTHONY STANSFIELD
发明人： ANTHONY STANSFIELD
IPC分类号： H03K19/177 , H05K13/00
CPC分类号： G01R31/318519 , G01R31/318533 , H03K19/17764 , Y10T29/49002
摘要： A functional logic block for embedding into a reconfigurable array, the functional logic block comprises at least one multi-bit register including a plurality of single-bit registers, the single-bit registers being divided into at least two groups. The functional logic block also comprises a shift chain for connecting each group of single-bit registers, each shift chain being arranged to connect its respective group of single-bit registers into a configuration and test chain.
摘要翻译：功能逻辑块用于嵌入到可重构阵列中，功能逻辑块包括至少一个多位寄存器，该多位寄存器包括多个单位寄存器，该单位寄存器被分成至少两组。功能逻辑块还包括用于连接每组单位寄存器的移位链，每个移位链被布置成将其相应的单位寄存器组连接到配置和测试链中。

2. 发明申请

US20050257024A1 Loosely-biased heterogeneous reconfigurable arrays 有权
标题翻译：松散偏差的异构可重构阵列
公开(公告)号：US20050257024A1
公开(公告)日：2005-11-17
申请号：US11130613
申请日：2005-05-16
申请人： Nicholas Ray , Andrea Olgiati , Anthony Stansfield , Alan Marshall
发明人： Nicholas Ray , Andrea Olgiati , Anthony Stansfield , Alan Marshall
IPC分类号： G06F15/78 , H03K19/173 , H03K19/177 , G06F15/00
CPC分类号： G06F9/3001 , G06F9/30181 , G06F9/3879 , G06F9/3897 , G06F15/7867 , H03K17/002 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： A heterogeneous array includes clusters of processing elements. The clusters include a combination of ALUs and multiplexers linked by direct connections and various general-purpose routing networks. The multiplexers are controlled by the ALUs in the same cluster, or alternatively by ALUs in other clusters, via a special purpose routing network. Components of applications configured onto the array are selectively implemented in either multiplexers or ALUs, as determined by the relative efficiency of implementing the component in one or the other type of processing element, and by the relative availability of the processing element types. Multiplexer control signals are generated from combinations of ALU status signals, and optionally routed to control multiplexers in different clusters.
摘要翻译：异构阵列包括处理元件群。集群包括通过直接连接和各种通用路由网络链接的ALU和多路复用器的组合。多路复用器由同一集群中的ALU或其他集群中的ALU通过专用路由网络控制。通过在一个或另一种类型的处理元件中实现组件的相对效率以及处理元件类型的相对可用性来确定，配置到阵列上的应用的组件被选择性地实现在多路复用器或ALU中。多路复用器控制信号从ALU状态信号的组合产生，并且可选地路由到不同簇中的控制多路复用器。

3. 发明授权

US07973554B2 Method of configuring embedded application-specific functional blocks 失效
标题翻译：配置嵌入式应用专用功能块的方法
公开(公告)号：US07973554B2
公开(公告)日：2011-07-05
申请号：US12042575
申请日：2008-03-05
申请人： Stuart Parry , Anthony Stansfield
发明人： Stuart Parry , Anthony Stansfield
IPC分类号： H03K19/173
CPC分类号： G06F17/5054
摘要： A method of configuring application-specific functional blocks embedded in a user programmable fabric, the user programmable fabric comprising configuration data control means having an input and an output and the application-specific functional blocks comprising configuration memory means having an input and an output. The method comprises the steps of sending configuration data to configure the application-specific functional block to the configuration control means of the user programmable fabric, routing the output of the configuration data control means of the user programmable fabric to the input of the configuration memory means of the application-specific functional blocks, transferring the configuration data to the configuration memory means of the application-specific functional blocks and configuring, using the configuration data, the application-specific functional blocks.
摘要翻译：一种配置嵌入在用户可编程结构中的应用专用功能块的方法，所述用户可编程结构包括具有输入和输出的配置数据控制装置以及包括具有输入和输出的配置存储器装置的应用专用功能块。该方法包括以下步骤：发送配置数据以将应用专用功能块配置到用户可编程结构的配置控制装置，将用户可编程结构的配置数据控制装置的输出路由到配置存储装置的输入将配置数据传送到应用专用功能块的配置存储器装置，并使用配置数据配置应用专用功能块。

4. 发明申请

US20100213975A1 COMBINED PROCESSING AND NON-VOLATILE MEMORY UNIT ARRAY 有权
标题翻译：组合处理和非易失性存储单元阵列
公开(公告)号：US20100213975A1
公开(公告)日：2010-08-26
申请号：US12713672
申请日：2010-02-26
申请人： Neil Price , Anthony STANSFIELD
发明人： Neil Price , Anthony STANSFIELD
IPC分类号： H03K19/173
CPC分类号： G06F15/7867 , G11C11/16 , H03K19/17728 , H03K19/1776
摘要： A reconfigurable logic device comprises an array of tiles interconnected through a routing network, each tile comprises both a processing unit including volatile configuration memory and a Random Access Memory unit.
摘要翻译：可重构逻辑设备包括通过路由网络互连的瓦片阵列，每个瓦片包括包括易失性配置存储器和随机存取存储器单元的处理单元。

5. 发明申请

US20100090720A1 FLEXIBLE PARALLEL/SERIAL RECONFIGURABLE ARRAY CONFIGURATION SCHEME 失效
标题翻译：灵活的并行/串行可重配置阵列配置方案
公开(公告)号：US20100090720A1
公开(公告)日：2010-04-15
申请号：US12576040
申请日：2009-10-08
申请人： Simon Deeley , Anthony Stansfield
发明人： Simon Deeley , Anthony Stansfield
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： G06F15/7867 , G06F15/8007
摘要： A programming interface device for a programmable logic circuit, the programmable logic circuit comprising a series of parallel logic block chains each having first and second connection means, the first and second connection means being disposed at opposite ends of each chain. The programming interface device comprising first and second interfacing means for interfacing with the first and second connection means of each logic block chain, respectively and at least one programming circuit, each programming circuit arranged to configure a plurality of serially connected logic blocks. Finally, the programming interface comprises programmable connection means for connecting the connection means of each logic block chain to either the connection means of another logic block chain or directly to one of the at least one programming circuits, such that the parallel logic block chains can be configured in parallel, series or in any combination thereof.
摘要翻译：一种用于可编程逻辑电路的编程接口装置，所述可编程逻辑电路包括一系列具有第一和第二连接装置的并行逻辑块链，所述第一和第二连接装置设置在每个链的相对端。编程接口设备包括分别与每个逻辑块链的第一和第二连接装置相连接的第一和第二接口装置和至少一个编程电路，每个编程电路被布置成配置多个串联的逻辑块。最后，编程接口包括可编程连接装置，用于将每个逻辑块链的连接装置连接到另一个逻辑块链的连接装置或直接连接至至少一个编程电路之一，使得并行逻辑块链可以是并联，串联或以任何组合构成。

6. 发明授权

US06820188B2 Method and apparatus for varying instruction streams provided to a processing device using masks 失效
标题翻译：用于改变使用掩模提供给处理装置的指令流的方法和装置
公开(公告)号：US06820188B2
公开(公告)日：2004-11-16
申请号：US10337596
申请日：2003-01-06
申请人： Anthony Stansfield , Alan David Marshall , Jean Vuillemin
发明人： Anthony Stansfield , Alan David Marshall , Jean Vuillemin
IPC分类号： G06F938
CPC分类号： G06F7/527 , G06F7/53 , G06F7/5338 , G06F9/30174 , G06F9/30178 , G06F9/30185 , G06F15/7867
摘要： A circuit is provided to provide instruction streams to a processing device: embodiments of the circuit are appropriate for use with RISC CPUs, whereas other embodiments are useable with other processing devices, such as small processing devices used in a field programmable array. The circuit receives an external instruction stream which provides a first set of instruction values, and has a memory which contains a second set of instruction values. Two or more outputs provide instruction streams to the processing device. The circuit has a control input in the form of a mask which causes a selection means to allocate bits from the first and second sets of instruction values to different instruction streams to the processing device.
摘要翻译：提供电路以向处理设备提供指令流：该电路的实施例适合于与RISC CPU一起使用，而其它实施例可用于其它处理设备，例如在现场可编程阵列中使用的小型处理设备。电路接收提供第一组指令值的外部指令流，并且具有包含第二组指令值的存储器。两个或多个输出向处理设备提供指令流。电路具有掩模形式的控制输入，其使选择装置将来自第一和第二组指令值的位分配给处理设备的不同指令流。

7. 发明授权

US06567834B1 Implementation of multipliers in programmable arrays 失效
标题翻译：实现可编程阵列中的乘法器
公开(公告)号：US06567834B1
公开(公告)日：2003-05-20
申请号：US09555624
申请日：2000-06-01
申请人： Alan David Marshall , Anthony Stansfield , Jean Vuillemin
发明人： Alan David Marshall , Anthony Stansfield , Jean Vuillemin
IPC分类号： G06F752
CPC分类号： G06F7/527 , G06F7/53 , G06F7/5338 , G06F9/30014 , G06F9/30036 , G06F9/3017 , G06F15/7867
摘要： Implementation of multipliers in an FPGA or similar device containing an array or other aggregation of small processor devices is a significant difficulty, leading to increased cost as a result of the silicon area consumed thereby. There is thus provided a method of multiplying a first number by a second number by use of an array of processing devices, each of said processing devices having a plurality of data inputs, a plurality of data outputs, and an instruction input for control of the function of the processing device, wherein said processing devices and an input for the first number and an input for the second number are interconnected by a freely configurable interconnect, and wherein each processing device calculates a partial product for multiplication of one or more bits of the first number with one or more bits of the second number, and for each processing device: the value received at the instruction input is determined by one or more bits of the first number; data inputs are provided by m bits of the second number, and, if appropriate, a carry input to add a carry from a less significant partial product and/or a summation input to sum all the partial products of the same significance; data outputs are provided as a summation output containing the least significant m bits of the partial product and a carry output containing any more significant bits of the partial product.
摘要翻译：在包含小型处理器设备的阵列或其他聚合的FPGA或类似设备中实现乘法器是一个重大困难，导致由于消耗的硅面积而导致的成本增加。因此，提供了一种通过使用处理装置阵列将第一数乘以第二数的方法，每个所述处理装置具有多个数据输入，多个数据输出和用于控制的指令输入其中所述处理装置和用于第一数量的输入和第二数量的输入通过可自由配置的互连互连，并且其中每个处理装置计算用于乘以所述第一数量的一个或多个比特的部分乘积第一号码，具有第二号码的一位或多位，并且对于每个处理设备：在指令输入处接收的值由第一号码的一位或多位确定; 数据输入由第二数量的m位提供，并且如果适当的话，提供进位输入以从较不重要的部分积和/或求和输入中添加进位以求具有相同重要性的所有部分乘积; 数据输出被提供为包含部分乘积的最低有效m位的求和输出和包含部分乘积的任何更高有效位的进位输出。

8. 发明授权

US06523107B1 Method and apparatus for providing instruction streams to a processing device 失效
标题翻译：用于向处理装置提供指令流的方法和装置
公开(公告)号：US06523107B1
公开(公告)日：2003-02-18
申请号：US09209532
申请日：1998-12-11
申请人： Anthony Stansfield , Alan David Marshall , Jean Vuillemin
发明人： Anthony Stansfield , Alan David Marshall , Jean Vuillemin
IPC分类号： G06F938
CPC分类号： G06F7/527 , G06F7/53 , G06F7/5338 , G06F9/30174 , G06F9/30178 , G06F9/30185 , G06F15/7867
摘要： A circuit is provided to provide instruction streams to a processing device: embodiments of the circuit are appropriate for use with RISC CPUs, whereas other embodiments are useable with other processing devices, such as small processing devices used in a field programmable array. The circuit receives an external instruction stream which provides a first set of instruction values, and has a memory which contains a second set of instruction values. Two or more outputs provide instruction streams to the processing device. The circuit has a control input in the form of a mask which causes a selection means to allocate bits from the first and second sets of instruction values to different instruction streams to the processing device.
摘要翻译：提供电路以向处理设备提供指令流：该电路的实施例适合于与RISC CPU一起使用，而其它实施例可用于其它处理设备，例如在现场可编程阵列中使用的小型处理设备。电路接收提供第一组指令值的外部指令流，并且具有包含第二组指令值的存储器。两个或多个输出向处理设备提供指令流。电路具有掩模形式的控制输入，其使选择装置将来自第一和第二组指令值的位分配给处理设备的不同指令流。

9. 外观设计

USD417737S Extruded post 失效
公开(公告)号：USD417737S
公开(公告)日：1999-12-14
申请号：US97085
申请日：1998-11-30
申请人： Anthony Stansfield
设计人： Anthony Stansfield

10. 发明授权

US08058896B2 Flexible parallel/serial reconfigurable array configuration scheme 失效
标题翻译：灵活的并行/串行可重配置阵列配置方案
公开(公告)号：US08058896B2
公开(公告)日：2011-11-15
申请号：US12576040
申请日：2009-10-08
申请人： Simon Deeley , Anthony Stansfield
发明人： Simon Deeley , Anthony Stansfield
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , H03K19/173
CPC分类号： G06F15/7867 , G06F15/8007
摘要： A programming interface device for a programmable logic circuit comprises a series of parallel logic block chains each having first and second connection means, the first and second connection means being disposed at opposite ends of each chain. The programming interface device comprises first and second interfacing means for interfacing with the first and second connection means of each logic block chain, respectively and at least one programming circuit, each programming circuit arranged to configure a plurality of serially connected logic blocks. Finally, the programming interface comprises programmable connection means for connecting the connection means of each logic block chain to either the connection means of another logic block chain or directly to one of the at least one programming circuits, such that the parallel logic block chains can be configured in parallel, series or in any combination thereof.
摘要翻译：一种用于可编程逻辑电路的编程接口装置包括一系列并行逻辑块链，每一个具有第一和第二连接装置，第一和第二连接装置设置在每个链的相对端。编程接口设备包括分别与每个逻辑块链的第一和第二连接装置和至少一个编程电路接口的第一和第二接口装置，每个编程电路被布置成配置多个串联的逻辑块。最后，编程接口包括可编程连接装置，用于将每个逻辑块链的连接装置连接到另一个逻辑块链的连接装置或直接连接至至少一个编程电路之一，使得并行逻辑块链可以是并联，串联或以任何组合构成。

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