专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4977498A Data processing system having a data memory interlock coherency scheme 失效
标题翻译：数据处理系统具有数据存储器互锁一致性方案
公开(公告)号：US4977498A
公开(公告)日：1990-12-11
申请号：US176785
申请日：1988-04-01
申请人： Joseph Rastegar , Anne S. Valiton
发明人： Joseph Rastegar , Anne S. Valiton
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0822 , G06F12/126
摘要： This invention is directed to a memory system that determines which blocks of a set of associative blocks in cache memory are unavailable for replacement. This is accomplished by operating the memory system to maintain a duplicate set of tags which track block ownership for this cache pursuant to a "snoopy" protocol. In addition, the cache system maintains a bit associated with each memory address to indicate whether any data blocks resident in it have been locked. The interlock status of the data blocks in the cache is not communicated to the memory system. Once a block is locked, it cannot be allocated for replacement until it is unlocked. When the cache system encounters a locked block, it skips over that block and allocates the next block of the associative blocks. From this, the memory system infers, by means of a replacement algorithm, that block is being locked and, therefore, cannot be replaced. This enables the memory system to implement an irregular replacement policy for this cache when the block to be replaced is owned and locked.
摘要翻译：本发明涉及一种存储器系统，其确定高速缓冲存储器中的一组相关块的哪些块不可用于替换。这是通过操作存储器系统来维护根据“窥探”协议跟踪该缓存的块所有权的重复标签集来实现的。此外，缓存系统保持与每个存储器地址相关联的位，以指示驻留在其中的任何数据块是否已被锁定。高速缓存中的数据块的互锁状态不传送到存储器系统。一旦块被锁定，在解锁之前不能分配块。当缓存系统遇到锁定块时，它跳过该块并分配关联块的下一个块。由此，存储器系统通过替换算法推断该块被锁定，因此不能被替换。这样，当要更换的块被拥有并被锁定时，这使得存储器系统能够为该缓存实现不规则的替换策略。

2. 发明授权

US4881165A Method and apparatus for high speed data transmission between two systems operating under the same clock with unknown and non constant skew in the clock between the two systems 失效
标题翻译：在两个系统之间进行高速数据传输的方法和装置，在两个系统之间的时钟中以相同的时钟运行，具有未知的和不恒定的偏差
公开(公告)号：US4881165A
公开(公告)日：1989-11-14
申请号：US176474
申请日：1988-04-01
申请人： David J. Sager , Anne S. Valiton , Jay C. Stickney , Raj K. Ramanujan
发明人： David J. Sager , Anne S. Valiton , Jay C. Stickney , Raj K. Ramanujan
IPC分类号： G06F1/10 , G06F13/42
CPC分类号： G06F1/10 , G06F13/4217
摘要： The invention is directed to a method by which data from a first synchronous subsystem is transmitted to a second synchronous subsystem physically spaced from the first subsystem such that the system clock is skewed relative to the two subsystems. Pursuant to the invention, the transmitted data cycle time is multiple of the common system cycle time and a clock signal is forwarded with the data from the first subsystem to the second subsystem. The clock signal forwarded with the data provides an indication to the second subsystem of the instants of time at which received data changes. The data change instants are used to generate a binary signal that inverts its value at each such instant. The binary signal is transmitted through a synchronizer to produce a logic signal in the second subsystem. The logic signal is utilized to transmit the received data into the second subsystem in synchronization with the clock of the second subsystem.
摘要翻译：本发明涉及一种方法，通过该方法将来自第一同步子系统的数据传输到与第一子系统物理间隔的第二同步子系统，使得系统时钟相对于两个子系统偏斜。根据本发明，发送的数据周期时间是公共系统周期时间的倍数，并且时钟信号与从第一子系统到第二子系统的数据一起转发。用数据转发的时钟信号向第二子系统提供接收到的数据变化的时刻的指示。数据变化时刻用于产生在每个这样的时刻反转其值的二进制信号。二进制信号通过同步器传输，以在第二子系统中产生逻辑信号。逻辑信号用于与第二子系统的时钟同步地将接收的数据发送到第二子系统。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式