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1. 发明申请

US20120187984A1 PREVENTING METASTABILITY OF A DIVIDE-BY-TWO QUADRATURE DIVIDER 有权
标题翻译：防止二分法二分法的均匀性
公开(公告)号：US20120187984A1
公开(公告)日：2012-07-26
申请号：US13010878
申请日：2011-01-21
申请人： Anirban Banerjee , Paul Scot Carlile , Zhenrong Jin
发明人： Anirban Banerjee , Paul Scot Carlile , Zhenrong Jin
IPC分类号： H03L7/00
CPC分类号： H03K21/023 , H03K23/54 , H03L7/18
摘要： Embodiments of the present invention provide an approach for receiving true and complement clock signals at high or low frequencies into inputs of a divide-by-two quadrature divider, and providing true and complement clock signals, which are one-half the measured frequencies of the clock input signals, at the output of the quadrature divider. A tri-state clock mux coupled with combinatorial reset logic, with pull-up and pull-down devices at the output of the tri-sate clock mux, and/or pull-up and pull-down devices between the quadrature divider latches provide a defined logic state during startup at the input of the quadrature divider. The defined logic state ensures the output of the quadrature divider is metastability-free during high frequency application. Specifically, the quadrature divider has two output clock signals that are true and complement with measured frequencies that are one-half of the measured frequencies of the two clock input signals coming into the quadrature divider.
摘要翻译：本发明的实施例提供了一种用于将高频或低频的真实和补码时钟信号接收到二分频正交分频器的输入端并提供真实和补码时钟信号的方法，这些信号是测量频率的二分之一时钟输入信号，在正交分频器的输出端。三态时钟复用器与组合复位逻辑耦合，在三态时钟复用器的输出端具有上拉和下拉器件，以及/或正交分压器锁存器之间的上拉和下拉器件提供了一个在正交分频器的输入端启动时定义逻辑状态。定义的逻辑状态确保正交分频器的输出在高频应用期间是无亚稳态的。具体来说，正交分频器具有两个输出时钟信号，这两个输出时钟信号是真实的，并且与测量的频率相乘，测量的频率是进入正交分频器的两个时钟输入信号的测量频率的一半。

2. 发明申请

US20100115278A1 SUPPORT OF MULTIPLE PRE-SHARED KEYS IN ACCESS POINT 有权
标题翻译：支持多个预共享密钥在接入点
公开(公告)号：US20100115278A1
公开(公告)日：2010-05-06
申请号：US12359987
申请日：2009-01-26
申请人： Hui Shen , Xiong Jiang , Anirban Banerjee , Hong Liu , Taroon Mandhana
发明人： Hui Shen , Xiong Jiang , Anirban Banerjee , Hong Liu , Taroon Mandhana
IPC分类号： H04L9/30
CPC分类号： H04L9/0844 , H04L63/061 , H04L2209/80 , H04W12/04 , H04W88/08
摘要： A method of operating an access point (AP) configured to support multiple pre-shared keys at a given time to authenticate its associated client devices. Each client device associated with the AP is provisioned with a key. To authenticate the client device tat attempts to connect to the AP, the AP determines which pre-shared key (PSK) of the multiple supported pre-shared keys (PSKs). if any, matches information including the key received from the client device. When the information matches, the client device is allowed to connect to the AP. Provisioning the AP with multiple PSKs allows selectively disconnecting associated client devices from the AP. The AP may be configured to support PSKs of different lifetime and complexity. Removing a PSK of the multiple PSKs supported by the AP and disconnecting a client device that uses this PSK does not disconnect other client devices using different keys to access the AP.
摘要翻译：一种操作接入点（AP）的方法，所述接入点（AP）被配置为在给定时间支持多个预共享密钥以验证其相关联的客户端设备。与AP关联的每个客户端设备都配置了一个密钥。为了验证客户端设备尝试连接到AP，AP确定多个支持的预共享密钥（PSK）的哪个预共享密钥（PSK）。如果有的话，匹配包括从客户端设备接收的密钥的信息。当信息匹配时，允许客户端设备连接到AP。为AP配置多个PSK可以有选择地断开与AP的关联的客户端设备。 AP可以被配置为支持不同寿命和复杂性的PSK。删除AP支持的多个PSK的PSK并断开使用此PSK的客户端设备不会使用不同的密钥断开其他客户端设备访问AP。

3. 发明授权

US07606945B2 Method and apparatus for dynamically configuring hardware resources by a generic CPU management interface 有权
标题翻译：通过CPU管理界面动态配置硬件资源的方法和装置
公开(公告)号：US07606945B2
公开(公告)日：2009-10-20
申请号：US11324222
申请日：2006-01-04
申请人： Vamsi M. Tatapudi , Anirban Banerjee
发明人： Vamsi M. Tatapudi , Anirban Banerjee
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： H04L49/109 , H04L49/3054
摘要： A programmable network component for use in a plurality of network devices with a shared architecture, where the programmable network component includes an interface with an external processing unit to provide management interface control between the external processing unit and a network device. The programmable network component also includes a plurality of internal busses each of which is coupled to the programmable network component and to at least one network component. The programmable network component further includes a plurality of external buses each of which is coupled to the programmable network component and to at least one physical interface. The programmable network component is configured to support a plurality of protocols for communication with a plurality of physical interface components and comprises a plurality of programmable registers for determining the status of the plurality of physical interfaces.
摘要翻译：一种用于具有共享架构的多个网络设备中的可编程网络组件，其中所述可编程网络组件包括与外部处理单元的接口，以在所述外部处理单元和网络设备之间提供管理接口控制。可编程网络组件还包括多个内部总线，每个内部总线被耦合到可编程网络组件和至少一个网络组件。可编程网络组件还包括多个外部总线，每个外部总线耦合到可编程网络组件和至少一个物理接口。可编程网络组件被配置为支持用于与多个物理接口组件通信的多个协议，并且包括用于确定多个物理接口的状态的多个可编程寄存器。

4. 发明申请

US20090146495A1 DESIGN STRUCTURE FOR A HIGH-SPEED LEVEL SHIFTER 有权
公开(公告)号：US20090146495A1
公开(公告)日：2009-06-11
申请号：US12350312
申请日：2009-01-08
申请人： Anirban Banerjee , Stephen F. Geissler , Shiu Chung Ho
发明人： Anirban Banerjee , Stephen F. Geissler , Shiu Chung Ho
IPC分类号： H02J1/00 , G06F17/50
CPC分类号： H03K19/018521 , Y10T307/50
摘要： Disclosed are embodiments of a design structure for a voltage level shifter circuit that operates without forward biasing junction diodes, regardless of the sequence in which different power supplies are powered up. The circuit embodiments incorporate a pair of series connected switches (e.g., transistors) between an input terminal and a voltage adjusting circuit. Each switch is controlled by a different supply voltage from a different power supply. Only when both power supplies are powered-up and the different supply voltages are received at both switches will a first signal generated using one of the supply voltages be passed to a voltage adjusting circuit and thereafter converted into a second signal representative of the first signal, but generated using the second supply voltage. Incorporation of the pair of series connected switches into the voltage level shifter circuit prevents forward biasing of junction diodes in the circuit and thereby prevents current leakage from the power supplies.

5. 发明申请

US20090109967A1 METHOD AND SYSTEM FOR REMOTELY CONFIGURING AN ETHERNET SWITCH USING ETHERNET PACKETS 审中-公开
标题翻译：使用以太网分组来远程配置以太网交换机的方法和系统
公开(公告)号：US20090109967A1
公开(公告)日：2009-04-30
申请号：US11931462
申请日：2007-10-31
申请人： Anirban Banerjee , Vamsi Tatapudi , Sarath Kumar Immadisetty
发明人： Anirban Banerjee , Vamsi Tatapudi , Sarath Kumar Immadisetty
IPC分类号： H04L12/56
CPC分类号： H04L49/351 , H04L41/0803 , H04L45/745 , H04L49/102 , H04L49/65
摘要： The disclosed systems and methods relate to remote configuration of an Ethernet Switch. Aspects of the present invention may reduce the time and cost associated with configuring and maintaining one or more Ethernet Switches in a network.
摘要翻译：所公开的系统和方法涉及以太网交换机的远程配置。本发明的方面可以减少与在网络中配置和维护一个或多个以太网交换机相关联的时间和成本。

6. 发明申请

US20090091368A1 DESIGN STRUCTURE FOR A HIGH-SPEED LEVEL SHIFTER 失效
标题翻译：高速水平变压器的设计结构
公开(公告)号：US20090091368A1
公开(公告)日：2009-04-09
申请号：US11869146
申请日：2007-10-09
申请人： Anirban Banerjee , Stephen F. Geissler , Shiu Chung Ho
发明人： Anirban Banerjee , Stephen F. Geissler , Shiu Chung Ho
IPC分类号： H03L5/00 , G06F17/50
CPC分类号： H03K19/018521 , Y10T307/50
摘要： Disclosed are embodiments of a design structure for a voltage level shifter circuit that operates without forward biasing junction diodes, regardless of the sequence in which different power supplies are powered up. The circuit embodiments incorporate a pair of series connected switches (e.g., transistors) between an input terminal and a voltage adjusting circuit. Each switch is controlled by a different supply voltage from a different power supply. Only when both power supplies are powered-up and the different supply voltages are received at both switches will a first signal generated using one of the supply voltages be passed to a voltage adjusting circuit and thereafter converted into a second signal representative of the first signal, but generated using the second supply voltage. Incorporation of the pair of series connected switches into the voltage level shifter circuit prevents forward biasing of junction diodes in the circuit and thereby prevents current leakage from the power supplies.
摘要翻译：公开了用于不经过正向偏置结二极管工作的电压电平移位器电路的设计结构的实施例，而不管不同电源供电的顺序如何。电路实施例在输入端和电压调节电路之间并入一对串联连接的开关（例如晶体管）。每个开关由不同电源的不同电源电压控制。只有当两个电源都通电并且在两个开关处接收不同的电源电压时，将使用一个电源电压产生的第一个信号传递到电压调节电路，然后转换成代表第一信号的第二信号，但是使用第二电源电压产生。将一对串联连接的开关并入电压电平移位器电路防止电路中结二极管的正向偏置，从而防止来自电源的电流泄漏。

7. 发明授权

US08856545B2 Security level determination of websites 有权
标题翻译：网站安全级别确定
公开(公告)号：US08856545B2
公开(公告)日：2014-10-07
申请号：US13183142
申请日：2011-07-14
申请人： Anirban Banerjee , Michalis Faloutsos
发明人： Anirban Banerjee , Michalis Faloutsos
IPC分类号： G06F11/30 , G06F11/00 , G06F21/00 , G06F12/14 , G08B23/00
CPC分类号： G06F21/00 , G06F21/577 , H04L63/14
摘要： A site analysis system to determine a security level of a website comprises a communication transceiver and a processing system. The communication transceiver is configured to receive content information associated with the website describing a current state of the website, receive historical event information associated with the website, and receive external information associated with the website from a source external to the website. The processing system is configured to process the content information to determine a content score for the website, process the historical event information and the external information to determine a reputational score for the website, and process the content score and the reputational score to generate a final score for the website.
摘要翻译：用于确定网站的安全级别的站点分析系统包括通信收发器和处理系统。通信收发器被配置为接收与网站相关联的内容信息，描述网站的当前状态，接收与网站相关联的历史事件信息，以及从网站外部的源接收与网站相关联的外部信息。处理系统被配置为处理内容信息以确定网站的内容分数，处理历史事件信息和外部信息以确定网站的声誉评分，并处理内容分数和声誉评分以产生最终的网站得分。

8. 发明授权

US08855087B2 Wireless access point supporting control by multiple applications 有权
标题翻译：无线接入点支持多种应用的控制
公开(公告)号：US08855087B2
公开(公告)日：2014-10-07
申请号：US12338277
申请日：2008-12-18
申请人： Anirban Banerjee , David A. Roberts , Hui Shen , Shawn Jiang , Saurabh Mahajan , Chris Gual
发明人： Anirban Banerjee , David A. Roberts , Hui Shen , Shawn Jiang , Saurabh Mahajan , Chris Gual
IPC分类号： H04W4/00 , H04B1/16 , H04L29/08 , H04W88/08
CPC分类号： H04L67/025 , H04L67/1095 , H04L67/34 , H04W48/12 , H04W76/27 , H04W88/08
摘要： A computing device configurable as a wireless network access point that can be controlled from multiple applications. The computing device provides an interface through which applications may input commands to change the state of the access point. The interface responds to these commands and other events, such as association or disassociation of a wireless client, in a manner that does not disrupt the applications or devices using the access point. To determine an appropriate response to any event, the interface may maintain state information, including a count of the number of applications and/or wireless devices that have taken action indicating an operating state of the wireless access point.
摘要翻译：可配置为可从多个应用程序控制的无线网络接入点的计算设备。计算设备提供了一个接口，通过该界面应用可以输入命令来改变接入点的状态。接口以不会中断使用接入点的应用或设备的方式响应这些命令和其他事件，例如无线客户端的关联或取消关联。为了确定对任何事件的适当响应，接口可以维护状态信息，包括已经采取指示无线接入点的操作状态的动作的应用和/或无线设备的数量的计数。

9. 发明授权

US08299823B2 Preventing metastability of a divide-by-two quadrature divider 有权
标题翻译：防止二分频正交分频器的亚稳态
公开(公告)号：US08299823B2
公开(公告)日：2012-10-30
申请号：US13010878
申请日：2011-01-21
申请人： Anirban Banerjee , Paul Scot Carlile , Zhenrong Jin
发明人： Anirban Banerjee , Paul Scot Carlile , Zhenrong Jin
IPC分类号： H03B19/00
CPC分类号： H03K21/023 , H03K23/54 , H03L7/18
摘要： Embodiments of the present invention provide an approach for receiving true and complement clock signals at high or low frequencies into inputs of a divide-by-two quadrature divider, and providing true and complement clock signals, which are one-half the measured frequencies of the clock input signals, at the output of the quadrature divider. A tri-state clock mux coupled with combinatorial reset logic, with pull-up and pull-down devices at the output of the tri-sate clock mux, and/or pull-up and pull-down devices between the quadrature divider latches provide a defined logic state during startup at the input of the quadrature divider. The defined logic state ensures the output of the quadrature divider is metastability-free during high frequency application. Specifically, the quadrature divider has two output clock signals that are true and complement with measured frequencies that are one-half of the measured frequencies of the two clock input signals coming into the quadrature divider.
摘要翻译：本发明的实施例提供了一种用于将高频或低频的真实和补码时钟信号接收到二分频正交分频器的输入端并提供真实和补码时钟信号的方法，这些信号是测量频率的二分之一时钟输入信号，在正交分频器的输出端。三态时钟复用器与组合复位逻辑耦合，在三态时钟复用器的输出端具有上拉和下拉器件，以及/或正交分压器锁存器之间的上拉和下拉器件提供了一个在正交分频器的输入端启动时定义逻辑状态。定义的逻辑状态确保正交分频器的输出在高频应用期间是无亚稳态的。具体来说，正交分频器具有两个输出时钟信号，这两个输出时钟信号是真实的，并且与测量的频率相乘，测量的频率是进入正交分频器的两个时钟输入信号的测量频率的一半。

10. 发明授权

US08244922B2 Method and apparatus for dynamically configuring hardware resources by a generic CPU management interface 失效
标题翻译：通过CPU管理界面动态配置硬件资源的方法和装置
公开(公告)号：US08244922B2
公开(公告)日：2012-08-14
申请号：US12578150
申请日：2009-10-13
申请人： Vamsi M. Tatapudi , Anirban Banerjee
发明人： Vamsi M. Tatapudi , Anirban Banerjee
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： H04L49/109 , H04L49/3054
摘要： A programmable network component for use in a plurality of network devices with a shared architecture, where the programmable network component includes an interface with an external processing unit to provide management interface control between the external processing unit and a network device. The programmable network component also includes a plurality of internal busses each of which is coupled to the programmable network component and to at least one network component. The programmable network component further includes a plurality of external buses each of which is coupled to the programmable network component and to at least one physical interface. The programmable network component is configured to support a plurality of protocols for communication with a plurality of physical interface components and comprises a plurality of programmable registers for determining the status of the plurality of physical interfaces.
摘要翻译：一种用于具有共享架构的多个网络设备中的可编程网络组件，其中所述可编程网络组件包括与外部处理单元的接口，以在所述外部处理单元和网络设备之间提供管理接口控制。可编程网络组件还包括多个内部总线，每个内部总线被耦合到可编程网络组件和至少一个网络组件。可编程网络组件还包括多个外部总线，每个外部总线耦合到可编程网络组件和至少一个物理接口。可编程网络组件被配置为支持用于与多个物理接口组件通信的多个协议，并且包括用于确定多个物理接口的状态的多个可编程寄存器。

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