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1. 发明授权

US06782501B2 System for reducing test data volume in the testing of logic products 有权
标题翻译：用于在逻辑产品测试中减少测试数据量的系统
公开(公告)号：US06782501B2
公开(公告)日：2004-08-24
申请号：US09972000
申请日：2001-10-05
申请人： Frank O. Distler , L. Owen Farnsworth , Andrew Ferko , Brion L. Keller , Bernd K. Koenemann
发明人： Frank O. Distler , L. Owen Farnsworth , Andrew Ferko , Brion L. Keller , Bernd K. Koenemann
IPC分类号： G06F1100
CPC分类号： G01R31/31921
摘要： A system for reducing test data volume in the testing of logic products such as modules on integrated circuit chips, and systems comprised of multiple integrated circuit chips. Test stimulus data are loaded from a tester into the logic product to apply to portions of combinational logic circuitry therein in order to detect faults comprises “care” bits and “non-care” bits. The care bits target focal faults of interest in the logic circuitry being tested while the non-care bits do not. Non-care bits in the test vector data are filled with repetitive, repeating, or other background data sequences. The background data sequences are constructed such that they can be algorithmically recovered from a small amount of initialization data. The recovery can use hardware that is located in the product under test, inside the tester, or between the product under test and the tester, or software residing in the tester and operating while the test is performed. The software and/or hardware recover the full test input stimulus data including the fill data from the much more compact source data. The use of a compacted data format for the fill data provides for a high degree of compressibility of the total test input stimulus vector data set. The method for test data reduction combines the compact data representation for the input stimulus data with on-product or off-product compression of the test response data. The response data compression can be accomplished by the use of error-detecting codes, by comparing the responses from several identical products under test. The combination of data compression techniques for both, test input stimulus data and test output response data, results in significantly better overall data reduction.
摘要翻译：用于减少诸如集成电路芯片上的模块的逻辑产品测试以及由多个集成电路芯片组成的系统的测试数据量的系统。测试刺激数据从测试器加载到逻辑产品中以应用于其中的组合逻辑电路的部分，以便检测包括“关心”位和“非关心”位的故障。护理位目标是正在测试的逻辑电路中的感兴趣的焦点故障，而无关位不存在。测试向量数据中的非关心位填充有重复的，重复的或其他背景数据序列。构建背景数据序列使得它们可以从少量的初始化数据被算术地恢复。恢复可以使用位于被测产品，测试仪内部，被测产品和测试仪之间的硬件，或者测试仪中存在的软件，并在测试时进行操作。软件和/或硬件从更紧凑的源数据中恢复包括填充数据的完整测试输入激励数据。对于填充数据使用压缩数据格式提供了总测试输入刺激矢量数据集的高度可压缩性。测试数据简化的方法将输入激励数据的紧凑数据表示与测试响应数据的产品或产品外压缩相结合。响应数据压缩可以通过使用错误检测代码，通过比较来自几个相同的被测产品的响应来实现。用于测试输入刺激数据和测试输出响应数据的数据压缩技术的组合导致显着更好的整体数据减少。

2. 发明申请

US20100235136A1 SYSTEM AND METHOD FOR AUTOMATICALLY GENERATING TEST PATTERNS FOR AT-SPEED STRUCTURAL TEST OF AN INTEGRATED CIRCUIT DEVICE USING AN INCREMENTAL APPROACH TO REDUCE TEST PATTERN COUNT 失效
标题翻译：用于自动生成集成电路设备的速度结构测试的测试模式的系统和方法，使用增量方法减少测试模式计数
公开(公告)号：US20100235136A1
公开(公告)日：2010-09-16
申请号：US12547637
申请日：2009-08-26
申请人： Robert W. Bassett , Andrew Ferko , Vikram Iyengar
发明人： Robert W. Bassett , Andrew Ferko , Vikram Iyengar
IPC分类号： G06F19/00 , G01R31/00
CPC分类号： G01R31/31835
摘要： Disclosed are embodiments of a system and method for automatically selecting and generating test patterns for an at-speed structural test of an integrated circuit device. Specifically, a test pattern generation pass is started and proceeds until the “knee” of the simulated test coverage curve is observed. Next, the test patterns are optionally reordered and some are removed. Then, another test pattern generation pass is started. The process is repeated iteratively until some predetermined final stopping criterion is met. By performing multiple test pattern generation passes and reducing the number of available test patterns that can be generated with each pass, the method exploits the initial increase in the test coverage curve inherent in each pass and limits the overall test pattern count.
摘要翻译：公开了用于自动选择和产生用于集成电路设备的高速结构测试的测试图案的系统和方法的实施例。具体地说，开始测试图形生成通过，并且直到观察到模拟测试覆盖曲线的“膝盖”为止。接下来，测试图案是可选地重新排序的，一些被去除。然后，开始另一个测试图形生成通过。该过程重复地重复，直到满足一些预定的最终停止标准。通过执行多个测试模式生成遍历并减少每次通过可生成的可用测试模式的数量，该方法利用了每次通过中固有的测试覆盖曲线的初始增加，并限制了整个测试模式计数。

3. 发明授权

US07103816B2 Method and system for reducing test data volume in the testing of logic products 有权
公开(公告)号：US07103816B2
公开(公告)日：2006-09-05
申请号：US09768121
申请日：2001-01-23
申请人： Frank O. Distler , Leonard O. Farnsworth, III , Andrew Ferko , Brion L. Keller , Bernd K. Koenemann , Donald L. Wheater
发明人： Frank O. Distler , Leonard O. Farnsworth, III , Andrew Ferko , Brion L. Keller , Bernd K. Koenemann , Donald L. Wheater
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31921
摘要： A method and system for reducing test data volume in the testing of logic products such as integrated circuit chips. Test data loaded by a tester into the logic product to apply to portions of combinational logic circuitry therein in order to detect faults comprises “care” bits and “non-care” bits. The care bits target focal faults of interest in the logic circuitry being tested while the non-care bits do not. According to the invention, non-care bits in the test vector data are filled with repetitive background data to provide for a high degree of compressibility of the test vector data. A substantial portion of the care bits may also be set to a repetitive value and the original values later recovered.

4. 发明授权

US08209141B2 System and method for automatically generating test patterns for at-speed structural test of an integrated circuit device using an incremental approach to reduce test pattern count 失效
标题翻译：用于自动生成用于集成电路设备的高速结构测试的测试模式的系统和方法，使用增量方法来减少测试图案计数
公开(公告)号：US08209141B2
公开(公告)日：2012-06-26
申请号：US12547637
申请日：2009-08-26
申请人： Robert W. Bassett , Andrew Ferko , Vikram Iyengar
发明人： Robert W. Bassett , Andrew Ferko , Vikram Iyengar
IPC分类号： G01R31/00 , G06F11/30
CPC分类号： G01R31/31835
摘要： Disclosed are embodiments of a system and method for automatically selecting and generating test patterns for an at-speed structural test of an integrated circuit device. Specifically, a test pattern generation pass is started and proceeds until the “knee” of the simulated test coverage curve is observed. Next, the test patterns are optionally reordered and some are removed. Then, another test pattern generation pass is started. The process is repeated iteratively until some predetermined final stopping criterion is met. By performing multiple test pattern generation passes and reducing the number of available test patterns that can be generated with each pass, the method exploits the initial increase in the test coverage curve inherent in each pass and limits the overall test pattern count.
摘要翻译：公开了用于自动选择和产生用于集成电路设备的高速结构测试的测试图案的系统和方法的实施例。具体地说，开始测试图形生成通过，并且直到观察到模拟测试覆盖曲线的“膝盖”为止。接下来，测试图案是可选地重新排序的，一些被去除。然后，开始另一个测试图形生成通过。该过程重复地重复，直到满足一些预定的最终停止标准。通过执行多个测试模式生成遍历并减少每次通过可生成的可用测试模式的数量，该方法利用了每次通过中固有的测试覆盖曲线的初始增加，并限制了整个测试模式计数。

5. 发明授权

US07900112B2 System and method for digital logic testing 有权
标题翻译：数字逻辑测试的系统和方法
公开(公告)号：US07900112B2
公开(公告)日：2011-03-01
申请号：US12173651
申请日：2008-07-15
申请人： Kenneth Pichamuthu , Prakash Venkitaraman , Andrew Ferko
发明人： Kenneth Pichamuthu , Prakash Venkitaraman , Andrew Ferko
IPC分类号： G01R31/28
CPC分类号： G06F11/261 , G01R31/318385 , G01R31/318511 , G06F11/263
摘要： Some embodiments provide a method of digital logic design and digital logic testing of logic under test, the logic including latches, the latches including measure latches, which are latches that measure focal faults more than other latches, and care bit latches, which are latches that require specific input values to test a fault, wherein a focal fault is a randomly selected untested fault in the logic under test, the method comprising generating test patterns for the logic under test; fault simulating the test patterns on the logic under test; ranking measure latches based on the number of focal faults they respectively measure; and tracing back a number of levels from at least some of the highest ranked measure latches and inserting test observe latches. Other methods and systems are also provided.
摘要翻译：一些实施例提供了一种用于测试逻辑的数字逻辑设计和数字逻辑测试的方法，包括锁存器的锁存器，包括测量锁存器的锁存器，其是比其他锁存器更多地测量局部故障的锁存器，以及护理位锁存器，需要特定的输入值来测试故障，其中焦点故障是被测逻辑中随机选择的未测试故障，该方法包括产生被测逻辑的测试模式; 模拟测试逻辑上的测试模式的故障; 基于他们分别测量的局灶性故障数量的排序测量锁存器; 并从至少一些最高排名的测量锁存器中追溯多个级别，并插入测试观察锁存器。还提供了其他方法和系统。

6. 发明申请

US20100017668A1 SYSTEM AND METHOD FOR DIGITAL LOGIC TESTING 有权
标题翻译：数字逻辑测试系统与方法
公开(公告)号：US20100017668A1
公开(公告)日：2010-01-21
申请号：US12173651
申请日：2008-07-15
申请人： Kenneth Pichamuthu , Prakash Venkitaraman , Andrew Ferko
发明人： Kenneth Pichamuthu , Prakash Venkitaraman , Andrew Ferko
IPC分类号： G06F11/00
CPC分类号： G06F11/261 , G01R31/318385 , G01R31/318511 , G06F11/263
摘要： Some embodiments provide a method of digital logic design and digital logic testing of logic under test, the logic including latches, the latches including measure latches, which are latches that measure focal faults more than other latches, and care bit latches, which are latches that require specific input values to test a fault, wherein a focal fault is a randomly selected untested fault in the logic under test, the method comprising generating test patterns for the logic under test; fault simulating the test patterns on the logic under test; ranking measure latches based on the number of focal faults they respectively measure; and tracing back a number of levels from at least some of the highest ranked measure latches and inserting test observe latches. Other methods and systems are also provided.
摘要翻译：一些实施例提供了一种用于测试逻辑的数字逻辑设计和数字逻辑测试的方法，包括锁存器的锁存器，包括测量锁存器的锁存器，其是比其他锁存器更多地测量局部故障的锁存器，以及护理位锁存器，需要特定的输入值来测试故障，其中焦点故障是被测逻辑中随机选择的未测试故障，该方法包括产生被测逻辑的测试模式; 模拟测试逻辑上的测试模式的故障; 基于他们分别测量的局灶性故障数量的排序测量锁存器; 并从至少一些最高排名的测量锁存器中追溯多个级别，并插入测试观察锁存器。还提供了其他方法和系统。

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