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1. 发明申请

US20150199517A1 UNIVERSAL EXTENSIBLE FIRMWARE INTERFACE MODULE IDENTIFICATION AND ANALYSIS 有权
标题翻译：通用可扩展的固件接口模块识别和分析
公开(公告)号：US20150199517A1
公开(公告)日：2015-07-16
申请号：US14598740
申请日：2015-01-16
申请人： Robert Allen Rose
发明人： Robert Allen Rose
IPC分类号： G06F21/57 , G06F21/56
CPC分类号： G06F21/57 , G06F21/562 , G06F21/575 , G06F2221/033 , G06F2221/034
摘要： The present disclosure provides a network architecture and verification platform for analyzing the various modules of a Unified Extensible Firmware Interface (UEFI) firmware image. In one embodiment, the disclosed network architecture and verification platform obtains various UEFI firmware images, such as UEFI firmware image residing on a client device or a UEFI firmware image hosted by a hardware manufacturer. The network architecture and verification platform may then segregate the various UEFI firmware modules that make up the UEFI firmware image, and subject the modules to different types of analysis. By analyzing the UEFI firmware modules individually, the network architecture and verification platform builds a repository of Globally Unique Identifiers (GUIDs) referenced by a given UEFI firmware module, which may then be referenced in future analyses to determine whether any changes, and the extent of such changes, have been made to an updated version of the given UEFI firmware module.
摘要翻译：本公开提供了一种用于分析统一可扩展固件接口（UEFI）固件映像的各种模块的网络架构和验证平台。在一个实施例中，所公开的网络架构和验证平台获得各种UEFI固件映像，例如驻留在客户端设备上的UEFI固件映像或由硬件制造商托管的UEFI固件映像。然后，网络架构和验证平台可以分离构成UEFI固件映像的各种UEFI固件模块，并使模块进行不同类型的分析。通过单独分析UEFI固件模块，网络架构和验证平台构建了由给定的UEFI固件模块引用的全局唯一标识符（GUID）的存储库，然后可以在将来的分析中引用它，以确定是否存在任何更改已经对给定的UEFI固件模块的更新版本进行了这种改变。

2. 发明授权

US6119116A System and method for accessing and distributing audio CD data over a network 失效
标题翻译：通过网络访问和分发音频CD数据的系统和方法
公开(公告)号：US6119116A
公开(公告)日：2000-09-12
申请号：US993114
申请日：1997-12-18
申请人： Robert Allen Rose
发明人： Robert Allen Rose
IPC分类号： G06F3/06 , G06F3/08 , G06F17/30 , G11B27/10 , G11B27/28 , H04H20/82 , G06F12/00
CPC分类号： G11B27/28 , G06F17/30067 , G11B27/105 , G11B2220/213 , G11B2220/2545 , Y10S707/916 , Y10S707/959 , Y10S707/99942 , Y10S707/99945
摘要： A system, method and computer program are provided in an installable file system (IFS) for a network server for enabling access to and distribution of Audio CD information over a client server network by creating a virtual directory of computer audio files from Table of Contents information read in raw sector mode from an audio CD in a CD-ROM drive, which virtual audio files appear to the server's operating system as normal files stored on a convention file system.
摘要翻译：在用于网络服务器的可安装文件系统（IFS）中提供了系统，方法和计算机程序，用于通过从目录信息创建计算机音频文件的虚拟目录来使得能够通过客户端服务器网络访问和分发音频CD信息从CD-ROM驱动器中的音频CD读入原始扇区模式，哪个虚拟音频文件作为常规文件存储在常规文件系统中作为服务器的操作系统显示。

3. 发明授权

US5642491A Method for expanding addressable memory range in real-mode processing to facilitate loading of large programs into high memory 失效
标题翻译：用于在实模式处理中扩展可寻址存储器范围以便于将大程序加载到高存储器中的方法
公开(公告)号：US5642491A
公开(公告)日：1997-06-24
申请号：US309862
申请日：1994-09-21
申请人： Robert Allen Rose , Allen Chester Wynn
发明人： Robert Allen Rose , Allen Chester Wynn
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G06F12/0292
摘要： Disclosed is a technique for overcoming the 1-Mbyte mode memory limitation associated with "real-mode" operation of certain Intel Corp. microprocessor architectures. This limitation can be overcome by altering the contents of a register portion that is computationally meaningful only in "protected mode," but which persists and exerts effects in real mode. By indirectly manipulating the contents of this register portion in protected mode in a manner that avoids disruption to the register during the switch back to real mode, access can be obtained, in real mode, to up to 4 Gbytes of volatile memory.
摘要翻译：公开了一种用于克服与某些英特尔公司微处理器架构的“实模式”操作相关的1兆字节模式存储器限制的技术。可以通过改变仅在“保护模式”下计算有意义的寄存器部分的内容，但是在实模式中持续存在并且施加效果可以克服该限制。通过以避免在切换回实模式期间对寄存器的中断的方式间接地以保护模式操纵该寄存器部分的内容，可以在实模式下获得高达4G字节的易失性存储器的访问。

4. 发明申请

US20090150642A1 Indexing Page Attributes 有权
标题翻译：索引页面属性
公开(公告)号：US20090150642A1
公开(公告)日：2009-06-11
申请号：US11950518
申请日：2007-12-05
申请人： Timothy Hume Heil , James Allen Rose , Andrew Henry Wottreng
发明人： Timothy Hume Heil , James Allen Rose , Andrew Henry Wottreng
IPC分类号： G06F12/10
CPC分类号： G06F12/0893 , G06F12/1009
摘要： Embodiments of the invention provide methods and apparatus for increasing the number of page attributes specified by a page table while minimizing an increase in size of the page table. According to embodiments of the invention, attribute index bits may be included within a page table and may be used to determine page attributes stored within an attribute index. Additionally, embodiments of the invention provide a plurality of new page attributes.
摘要翻译：本发明的实施例提供了用于增加由页表指定的页面属性的数量的方法和装置，同时最小化页表的大小的增加。根据本发明的实施例，属性索引位可以包括在页表内，并且可以用于确定存储在属性索引内的页面属性。另外，本发明的实施例提供了多个新的页面属性。

5. 发明申请

US20050062460A1 Time division multiplexed optical measuring system 失效
标题翻译：时分复用光学测量系统
公开(公告)号：US20050062460A1
公开(公告)日：2005-03-24
申请号：US10931446
申请日：2004-09-01
申请人： Jame Blake , Farnoosh Rahmatian , Allen Rose
发明人： Jame Blake , Farnoosh Rahmatian , Allen Rose
IPC分类号： G01R15/24 , G01R31/00
CPC分类号： G01D5/268 , G01R15/247 , H04Q9/00
摘要： A time division multiplexed optical voltage measuring system includes an optical voltage sensing system module including, (i) a plurality of optical sensors where each sensor is responsive to an input interrogation light wave, and (ii) one or more optical outputs affected by sensed electric field thereat. The optical voltage sensing system module includes an optical circuit arrangement having (i) an input for receiving a module specific pulsed light wave derived from a primary pulsed light wave from a remote light source, and (ii) arranged such that each of the plurality of optical sensors receives an interrogation pulsed light wave. The optical circuit arrangement of the optical voltage sensing system module further includes at least one optical wave combiner for combining like-kind of outputs from all of the plurality of optical sensors. The optical circuit is arranged such that the pulsed light waves from the outputs of different optical sensors arrive at the optical wave combiner at differing times. In turn, the output of the combiner is passed to a detector and signal processor at a remote location for signal processing, and providing a measurement of the voltage intended to be measured. In a specific embodiment, each voltage sensing modules is arranged integral with a high voltage insulator column of a multi-phase power line system.
摘要翻译：时分复用光电压测量系统包括光电压检测系统模块，该光电压检测系统模块包括：（i）多个光学传感器，其中每个传感器响应于输入询问光波，以及（ii）一个或多个受感测电在那里光电压检测系统模块包括光电路装置，该光电路装置具有：（i）用于接收源自远程光源的主脉冲光波的模块专用脉冲光波的输入，以及（ii）布置成使得多个光学传感器接收询问脉冲光波。光电压检测系统模块的光电路布置还包括至少一个光波组合器，用于组合来自所有多个光学传感器的类似类型的输出。光路布置成使得来自不同光学传感器的输出的脉冲光波在不同时间到达光波合成器。反过来，组合器的输出又传递到远程位置处的检测器和信号处理器进行信号处理，并提供要测量的电压的测量值。在具体实施例中，每个电压感测模块与多相电力线系统的高压绝缘子列一体化。

6. 发明授权

US06314500B1 Selective routing of data in a multi-level memory architecture based on source identification information 有权
标题翻译：基于源标识信息在多级存储器体系结构中选择性地选择数据
公开(公告)号：US06314500B1
公开(公告)日：2001-11-06
申请号：US09228314
申请日：1999-01-11
申请人： James Allen Rose
发明人： James Allen Rose
IPC分类号： G06F1200
CPC分类号： G06F12/0813
摘要： A data processing system, circuit arrangement, integrated circuit device, program product, and method utilize source identification information to selectively route data to different memory sources in a shared memory system. This permits, for example, data to be routed to only a portion of the memory sources associated with a given requester, thereby reducing the bandwidth to other memory sources and reducing overall latencies within the system. Among other possible information, the source identification information may include an identification of which memory source and/or which level of memory is providing the requested data, and/or an indication of what processor/requester and/or what type of instruction last modified the requested data.
摘要翻译：数据处理系统，电路布置，集成电路设备，程序产品和方法利用源标识信息来选择性地将数据路由到共享存储器系统中的不同存储器源。这允许例如将数据路由到仅与给定请求者相关联的一部分存储器源，从而减少对其他存储器源的带宽并减少系统内的总延迟。在其他可能的信息中，源识别信息可以包括哪个存储器源和/或哪个级别的存储器提供所请求的数据的标识，和/或什么处理器/请求者和/或上一次修改什么类型的指令的指示请求的数据。

7. 发明授权

US5845318A Dasd I/O caching method and application including replacement policy minimizing data retrieval and storage costs 失效
标题翻译： Dasd I / O缓存方法和应用程序，包括替换策略最小化数据检索和存储成本
公开(公告)号：US5845318A
公开(公告)日：1998-12-01
申请号：US738851
申请日：1996-10-28
申请人： Robert Allen Rose , Joseph Harry Nord
发明人： Robert Allen Rose , Joseph Harry Nord
IPC分类号： G06F12/08 , G06F12/12 , G06F12/00
CPC分类号： G06F12/0866 , G06F12/121
摘要： The performance of a DASD having a data cache and at least one set of R/W heads is improved by implementing a replacement policy which, upon determining that a request for data in the DASD requires replacement of a data in a data cache buffer, selects cache data corresponding to data which is cheapest to retrieve from the DASD in view of a location of the DASD R/W heads and replaces the selected cache data with the requested data, thus keeping the cache filled with data which is least expensive to retrieve from the DASD. Data in the DASD is updated from the cache when it is inexpensive.
摘要翻译：具有数据高速缓存和至少一组R / W头的DASD的性能通过实施替换策略得到改进，该替换策略在确定DASD中的数据请求需要替换数据高速缓冲存储器中的数据时，选择鉴于DASD R / W头的位置，对应于最便宜的从DASD检索的数据的高速缓存数据，并用所请求的数据替换所选择的高速缓存数据，从而保持高速缓冲存储器填满从 DASD。 DASD中的数据在低成本时从缓存中更新。

8. 发明授权

US6049867A Method and system for multi-thread switching only when a cache miss occurs at a second or higher level 失效
标题翻译：只有当第二级或更高级别发生高速缓存未命中时，多线程切换的方法和系统
公开(公告)号：US6049867A
公开(公告)日：2000-04-11
申请号：US906228
申请日：1997-08-04
申请人： Richard James Eickemeyer , Ross Evan Johnson , Harold F. Kossman , Steven Raymond Kunkel , Timothy John Mullins , James Allen Rose
发明人： Richard James Eickemeyer , Ross Evan Johnson , Harold F. Kossman , Steven Raymond Kunkel , Timothy John Mullins , James Allen Rose
IPC分类号： G06F9/38 , G06F9/48 , G06F12/08
CPC分类号： G06F9/4881 , G06F12/0811 , G06F12/0842 , G06F9/3851
摘要： A method and system for enhanced performance multithread operation in a data processing system which includes a processor, a main memory store and at least two levels of cache memory. At least one instruction within an initial thread is executed. Thereafter, the state of the processor at a selected point within the first thread is stored, execution of the first thread is terminated and a second thread is selected for execution only in response to a level two or higher cache miss, thereby minimizing processor delays due to memory latency. The validity state of each thread is preferably maintained in order to minimize the likelihood of returning to a prior thread for execution before the cache miss has been corrected. A least recently executed thread is preferably selected for execution in the event of a nonvalidity indication in association with all remaining threads, in anticipation of a change to the valid status of that thread prior to all other threads. A thread switch bit may also be utilized to selectively inhibit thread switching where execution of a particular thread is deemed necessary.
摘要翻译：一种用于在数据处理系统中增强性能多线程操作的方法和系统，其包括处理器，主存储器存储器和至少两个级别的高速缓冲存储器。执行初始线程内的至少一条指令。此后，存储处于第一线程内的选定点的处理器的状态，终止第一线程的执行，并且仅响应于二级或更高级别的高速缓存未命中而选择执行第二线程，从而最小化处理器延迟到内存延迟。优选地保持每个线程的有效性状态，以便在高速缓存未命中被校正之前最小化返回到先前线程执行的可能性。在所有其他线程之前，对于线程的有效状态的改变，优选地，在与所有剩余线程相关联的非有效性指示的情况下，选择最不执行的线程用于执行。线程切换位也可用于选择性地禁止线程切换，其中特定线程的执行被认为是必要的。

9. 发明授权

US08028118B2 Using an index value located on a page table to index page attributes 有权
标题翻译：使用页表上的索引值来索引页面属性
公开(公告)号：US08028118B2
公开(公告)日：2011-09-27
申请号：US11950518
申请日：2007-12-05
申请人： Timothy Hume Heil , James Allen Rose , Andrew Henry Wottreng
发明人： Timothy Hume Heil , James Allen Rose , Andrew Henry Wottreng
IPC分类号： G06F12/10
CPC分类号： G06F12/0893 , G06F12/1009
摘要： Embodiments of the invention provide methods and apparatus for increasing the number of page attributes specified by a page table while minimizing an increase in size of the page table. According to embodiments of the invention, attribute index bits may be included within a page table and may be used to determine page attributes stored within an attribute index. Additionally, embodiments of the invention provide a plurality of new page attributes.
摘要翻译：本发明的实施例提供了用于增加由页表指定的页面属性的数量的方法和装置，同时最小化页表的大小的增加。根据本发明的实施例，属性索引位可以包括在页表内，并且可以用于确定存储在属性索引内的页面属性。另外，本发明的实施例提供了多个新的页面属性。

10. 发明授权

US07739477B2 Multiple page size address translation incorporating page size prediction 有权
标题翻译：多页尺寸地址转换结合页面大小预测
公开(公告)号：US07739477B2
公开(公告)日：2010-06-15
申请号：US11733520
申请日：2007-04-10
申请人： Jeffrey Powers Bradford , Jason Nathaniel Dale , Kimberly Marie Fernsler , Timothy Hume Heil , James Allen Rose
发明人： Jeffrey Powers Bradford , Jason Nathaniel Dale , Kimberly Marie Fernsler , Timothy Hume Heil , James Allen Rose
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/26 , G06F9/34
CPC分类号： G06F12/1036 , G06F2212/652
摘要： Page size prediction is used to predict a page size for a page of memory being accessed by a memory access instruction such that the predicted page size can be used to access an address translation data structure. By doing so, an address translation data structure may support multiple page sizes in an efficient manner and with little additional circuitry disposed in the critical path for address translation, thereby increasing performance.
摘要翻译：页面大小预测用于预测由存储器访问指令访问的存储器页面的页面大小，使得可以使用预测的页面大小来访问地址转换数据结构。通过这样做，地址转换数据结构可以以有效的方式支持多个页面大小，并且在关键路径中设置少量额外的电路用于地址转换，从而提高性能。

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