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1. 发明授权

US09287209B2 Metal finger capacitor for high-K metal gate processes 有权
标题翻译：金属制电容器用于高K金属栅极工艺
公开(公告)号：US09287209B2
公开(公告)日：2016-03-15
申请号：US13338492
申请日：2011-12-28
申请人： Agnes Neves Woo , Pascal Tran , Akira Ito , Guang-Jye Shiau , Chao-Yang Lu , Jung Wang
发明人： Agnes Neves Woo , Pascal Tran , Akira Ito , Guang-Jye Shiau , Chao-Yang Lu , Jung Wang
IPC分类号： H01L23/522 , H01L27/02 , H01L27/01 , H01L49/02
CPC分类号： H01L23/5223 , H01L23/522 , H01L23/5222 , H01L23/5225 , H01L27/016 , H01L27/0207 , H01L28/86 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： Embodiments described herein provide a structure for finger capacitors, and more specifically metal-oxide-metal (“MOM”) finger capacitors and arrays of finger capacitors. A plurality of Shallow Trench Isolation (STI) formations is associated with every other column of capacitor fingers, with poly fill formations covering the STI formations to provide a more robust and efficient structure.
摘要翻译：本文描述的实施例提供了用于手指电容器，更具体地金属氧化物金属（“MOM”）指状电容器和指状电容器阵列的结构。多个浅沟槽隔离（STI）结构与电容器手指的每隔一列相关联，多层填充层覆盖STI构造以提供更坚固和更有效的结构。

2. 发明授权

US08289046B2 Switchable passive termination circuits 有权
标题翻译：可切换无源终端电路
公开(公告)号：US08289046B2
公开(公告)日：2012-10-16
申请号：US13173706
申请日：2011-06-30
申请人： Joseph Aziz , Andrew Chen , Derek Tam , Ark-Chew Wong , Agnes Neves Woo , Marcel Lugthart
发明人： Joseph Aziz , Andrew Chen , Derek Tam , Ark-Chew Wong , Agnes Neves Woo , Marcel Lugthart
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04L25/0298
摘要： According to one exemplary embodiment, an active termination circuit includes at least one active termination branch, where the at least one active termination branch includes at least one transistor for providing an active termination output. The at least one active termination branch further includes an amplifier driving the at least one transistor, where the amplifier has a non-inverting input coupled to the active termination output via a feedback network. The amplifier controls a current flowing through the at least one transistor so as to provide the active termination output. The active termination output can be provided at a drain of the at least one transistor, where a source of the at least one transistor is coupled to ground through a degeneration transistor and a tail current sink.
摘要翻译：根据一个示例性实施例，有源终端电路包括至少一个有源终端分支，其中所述至少一个有源终端分支包括用于提供有源终端输出的至少一个晶体管。所述至少一个有源终端分支还包括驱动所述至少一个晶体管的放大器，其中所述放大器具有经由反馈网络耦合到所述有源终端输出的非反相输入。放大器控制流过至少一个晶体管的电流，以便提供有源终端输出。可以在至少一个晶体管的漏极处提供有源终端输出，其中至少一个晶体管的源极通过退化晶体管和尾部电流吸收器耦合到地。

3. 发明授权

US07439592B2 ESD protection for high voltage applications 有权
标题翻译： ESD保护用于高压应用
公开(公告)号：US07439592B2
公开(公告)日：2008-10-21
申请号：US11198277
申请日：2005-08-08
申请人： Agnes Neves Woo
发明人： Agnes Neves Woo
IPC分类号： H01L23/62
CPC分类号： H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： An ESD device includes a low doped well connected to a first contact and a diffusion area connected to a second contact. A substrate between the low doped well and the diffusion area has a dopant polarity that is opposite a dopant polarity of the low doped well and the diffusion area. A distance between the low doped well and the diffusion area determines a triggering voltage of the ESD device. A depletion region is formed between the low doped well and the substrate when a reverse bias voltage is applied to the ESD device. A current discharging path is formed between the first contact and the second contact when the depletion region comes in to contact with the diffusion area. The substrate is biased by a connection to the second contact. Alternatively, an additional diffusion area with the same dopant polarity, connected to a third contact, biases the substrate.
摘要翻译： ESD器件包括连接到第一触点的低掺杂阱和连接到第二触点的扩散区。低掺杂阱和扩散区之间的衬底具有与低掺杂阱和扩散区的掺杂剂极性相反的掺杂剂极性。低掺杂阱和扩散区之间的距离决定了ESD器件的触发电压。当向ESD器件施加反向偏置电压时，在低掺杂阱和衬底之间形成耗尽区。当耗尽区域与扩散区域接触时，在第一触点和第二触点之间形成电流放电路径。衬底通过与第二接触件的连接来偏置。或者，连接到第三接触件的具有相同掺杂剂极性的附加扩散区域偏压衬底。

4. 发明申请

US20090161276A1 ESD Configuration for Low Parasitic Capacitance I/O 有权
标题翻译：低寄生电容I / O的ESD配置
公开(公告)号：US20090161276A1
公开(公告)日：2009-06-25
申请号：US12393417
申请日：2009-02-26
申请人： Chun-Ying CHEN , Agnes Neves Woo
发明人： Chun-Ying CHEN , Agnes Neves Woo
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An integrated circuit can include an I/O pad, an internal circuit, an inductor, an electrostatic discharge (ESD) protection circuit, and an ESD clamp. The internal circuit can be biased with a first voltage supply and a second voltage supply, where the internal circuit is connected to the I/O pad at a first node. The ESD protection circuit can be connected between the first node and a second node. The inductor can be connected between the second node and a third voltage supply. Further, the ESD clamp can be connected between the second node and the second voltage supply.
摘要翻译：集成电路可以包括I / O焊盘，内部电路，电感器，静电放电（ESD）保护电路和ESD钳位。内部电路可以用第一电压源和第二电压源进行偏置，其中内部电路在第一节点处连接到I / O焊盘。 ESD保护电路可以连接在第一节点和第二节点之间。电感器可以连接在第二节点和第三电压源之间。此外，ESD钳位可以连接在第二节点和第二电压源之间。

5. 发明申请

US20090045464A1 ESD protection for high voltage applications 有权
标题翻译： ESD保护用于高压应用
公开(公告)号：US20090045464A1
公开(公告)日：2009-02-19
申请号：US12285679
申请日：2008-10-10
申请人： Agnes Neves Woo
发明人： Agnes Neves Woo
IPC分类号： H01L23/62 , H01L21/30
CPC分类号： H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： An ESD device includes a low doped well connected to a first contact and a diffusion area connected to a second contact. A substrate between the low doped well and the diffusion area has a dopant polarity that is opposite a dopant polarity of the low doped well and the diffusion area. A distance between the low doped well and the diffusion area determines a triggering voltage of the ESD device. A depletion region is formed between the low doped well and the substrate when a reverse bias voltage is applied to the ESD device. A current discharging path is formed between the first contact and the second contact when the depletion region comes in to contact with the diffusion area. The substrate is biased by a connection to the second contact. Alternatively, an additional diffusion area with the same dopant polarity, connected to a third contact, biases the substrate.
摘要翻译： ESD器件包括连接到第一触点的低掺杂阱和连接到第二触点的扩散区。低掺杂阱和扩散区之间的衬底具有与低掺杂阱和扩散区的掺杂剂极性相反的掺杂剂极性。低掺杂阱和扩散区之间的距离决定了ESD器件的触发电压。当向ESD器件施加反向偏置电压时，在低掺杂阱和衬底之间形成耗尽区。当耗尽区域与扩散区域接触时，在第一触点和第二触点之间形成电流放电路径。衬底通过与第二接触件的连接来偏置。或者，连接到第三接触件的具有相同掺杂剂极性的附加扩散区域偏压衬底。

6. 发明申请

US20130113077A1 Metal Finger Capacitor for High-K Metal Gate Processes 有权
标题翻译：金属手指电容器用于高K金属栅极工艺
公开(公告)号：US20130113077A1
公开(公告)日：2013-05-09
申请号：US13338492
申请日：2011-12-28
申请人： Agnes Neves WOO , Pascal Tran , Akira Ito , Guang-Jye Shiau , Chao-Yang Lu , Jung Wang
发明人： Agnes Neves WOO , Pascal Tran , Akira Ito , Guang-Jye Shiau , Chao-Yang Lu , Jung Wang
IPC分类号： H01L29/02
CPC分类号： H01L23/5223 , H01L23/522 , H01L23/5222 , H01L23/5225 , H01L27/016 , H01L27/0207 , H01L28/86 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： Embodiments described herein provide a structure for finger capacitors, and more specifically metal-oxide-metal (“MOM”) finger capacitors and arrays of finger capacitors. A plurality of Shallow Trench Isolation (STI) formations is associated with every other column of capacitor fingers, with poly fill formations covering the STI formations to provide a more robust and efficient structure.
摘要翻译：本文描述的实施例提供了用于手指电容器，更具体地金属氧化物金属（“MOM”）指状电容器和指状电容器阵列的结构。多个浅沟槽隔离（STI）结构与电容器手指的每隔一列相关联，多层填充层覆盖STI构造以提供更坚固和更有效的结构。

7. 发明授权

US07920366B2 ESD configuration for low parasitic capacitance I/O 有权
标题翻译： ESD配置用于低寄生电容I / O
公开(公告)号：US07920366B2
公开(公告)日：2011-04-05
申请号：US12393417
申请日：2009-02-26
申请人： Chun-Ying Chen , Agnes Neves Woo
发明人： Chun-Ying Chen , Agnes Neves Woo
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： An integrated circuit can include an I/O pad, an internal circuit, an inductor, an electrostatic discharge (ESD) protection circuit, and an ESD clamp. The internal circuit can be biased with a first voltage supply and a second voltage supply, where the internal circuit is connected to the I/O pad at a first node. The ESD protection circuit can be connected between the first node and a second node. The inductor can be connected between the second node and a third voltage supply. Further, the ESD clamp can be connected between the second node and the second voltage supply.
摘要翻译：集成电路可以包括I / O焊盘，内部电路，电感器，静电放电（ESD）保护电路和ESD钳位。内部电路可以用第一电压源和第二电压源进行偏置，其中内部电路在第一节点处连接到I / O焊盘。 ESD保护电路可以连接在第一节点和第二节点之间。电感器可以连接在第二节点和第三电压源之间。此外，ESD钳位可以连接在第二节点和第二电压源之间。

8. 发明申请

US20100259340A1 Active termination and switchable passive termination circuits 有权
标题翻译：主动终端和可切换无源终端电路
公开(公告)号：US20100259340A1
公开(公告)日：2010-10-14
申请号：US12384793
申请日：2009-04-08
申请人： Joseph Aziz , Andrew Chen , Derek Tam , Ark-Chew Wong , Agnes Neves Woo , Marcel Lugthart
发明人： Joseph Aziz , Andrew Chen , Derek Tam , Ark-Chew Wong , Agnes Neves Woo , Marcel Lugthart
IPC分类号： H03H7/38
CPC分类号： H04L25/0298
摘要： According to one exemplary embodiment, an active termination circuit includes at least one active termination branch, where the at least one active termination branch includes at least one transistor for providing an active termination output. The at least one active termination branch further includes an amplifier driving the at least one transistor, where the amplifier has a non-inverting input coupled to the active termination output via a feedback network. The amplifier controls a current flowing through the at least one transistor so as to provide the active termination output. The active termination output can be provided at a drain of the at least one transistor, where a source of the at least one transistor is coupled to ground through a degeneration transistor and a tail current sink.
摘要翻译：根据一个示例性实施例，有源终端电路包括至少一个有源终端分支，其中所述至少一个有源终端分支包括用于提供有源终端输出的至少一个晶体管。所述至少一个有源终端分支还包括驱动所述至少一个晶体管的放大器，其中所述放大器具有经由反馈网络耦合到所述有源终端输出的非反相输入。放大器控制流过至少一个晶体管的电流，以便提供有源终端输出。可以在至少一个晶体管的漏极处提供有源终端输出，其中至少一个晶体管的源极通过退化晶体管和尾部电流吸收器耦合到地。

9. 发明授权

US07505238B2 ESD configuration for low parasitic capacitance I/O 失效
标题翻译： ESD配置用于低寄生电容I / O
公开(公告)号：US07505238B2
公开(公告)日：2009-03-17
申请号：US11174731
申请日：2005-07-06
申请人： Agnes Neves Woo , Chun-Ying Chen
发明人： Agnes Neves Woo , Chun-Ying Chen
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： An I/O ESD protection configuration of an integrated circuit that includes an ESD protection circuit connected between an I/O pad and an internal circuit at a first node and to an inductor at a second node. The inductor is connected between the second node and an external power supply. The external power supply provides a high reverse bias voltage across a diode of the ESD protection circuit. An ESD clamp is connected between the second node and a ground. An ESD discharge current is shunted through the ESD protection circuit and through the ESD clamp during a positive I/O ESD event. The inductor can be chosen to tune out a parasitic capacitance of the ESD clamp. The inductor can also block high frequency signals between the I/O pad and the external power supply, thereby minimizing the parasitic capacitance of the diode of the ESD protection circuit at high frequency.
摘要翻译：集成电路的I / O ESD保护配置，其包括连接在第一节点处的I / O焊盘和内部电路之间的ESD保护电路以及第二节点处的电感器。电感器连接在第二节点和外部电源之间。外部电源在ESD保护电路的二极管上提供高反向偏置电压。 ESD钳位器连接在第二节点和地之间。在正I / O ESD事件期间，ESD放电电流通过ESD保护电路并通过ESD钳位分流。可以选择电感来调整ESD钳位的寄生电容。电感器还可以阻挡I / O焊盘和外部电源之间的高频信号，从而最大限度地降低ESD保护电路在高频下的二极管的寄生电容。

10. 发明授权

US08049278B2 ESD protection for high voltage applications 有权
标题翻译： ESD保护用于高压应用
公开(公告)号：US08049278B2
公开(公告)日：2011-11-01
申请号：US12285679
申请日：2008-10-10
申请人： Agnes Neves Woo
发明人： Agnes Neves Woo
IPC分类号： H01L23/62 , H01L21/8238
CPC分类号： H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： An ESD device includes a low doped well connected to a first contact and a diffusion area connected to a second contact. A substrate between the low doped well and the diffusion area has a dopant polarity that is opposite a dopant polarity of the low doped well and the diffusion area. A distance between the low doped well and the diffusion area determines a triggering voltage of the ESD device. A depletion region is formed between the low doped well and the substrate when a reverse bias voltage is applied to the ESD device. A current discharging path is formed between the first contact and the second contact when the depletion region comes in to contact with the diffusion area. The substrate is biased by a connection to the second contact. Alternatively, an additional diffusion area with the same dopant polarity, connected to a third contact, biases the substrate.
摘要翻译： ESD器件包括连接到第一触点的低掺杂阱和连接到第二触点的扩散区。低掺杂阱和扩散区之间的衬底具有与低掺杂阱和扩散区的掺杂剂极性相反的掺杂剂极性。低掺杂阱和扩散区之间的距离决定了ESD器件的触发电压。当向ESD器件施加反向偏置电压时，在低掺杂阱和衬底之间形成耗尽区。当耗尽区域与扩散区域接触时，在第一触点和第二触点之间形成电流放电路径。衬底通过与第二接触件的连接来偏置。或者，连接到第三接触件的具有相同掺杂剂极性的附加扩散区域偏压衬底。

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