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1. 发明授权

US08862966B2 Adjustment of write timing based on error detection techniques 有权
标题翻译：基于错误检测技术调整写时序
公开(公告)号：US08862966B2
公开(公告)日：2014-10-14
申请号：US12846958
申请日：2010-07-30
申请人： Aaron John Nygren , Ming-Ju Edward Lee , Shadi M. Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger
发明人： Aaron John Nygren , Ming-Ju Edward Lee , Shadi M. Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger
IPC分类号： H03M13/00 , G06F13/42
CPC分类号： G06F13/4243
摘要： A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于基于错误检测功能的结果来调整存储器件中的写入定时。例如，该方法可以包括基于错误检测功能的结果来确定数据总线上的信号与写入时钟信号之间的写时序窗口。该方法还可以包括基于写时序窗口调整数据总线上的信号与写时钟信号之间的相位差。存储器件可以基于调整后的相位差来恢复数据总线上的数据。

2. 发明授权

US07844888B2 Electronic device, method for operating an electronic device, memory circuit and method of operating a memory circuit 有权
标题翻译：电子设备，操作电子设备的方法，存储器电路和操作存储器电路的方法
公开(公告)号：US07844888B2
公开(公告)日：2010-11-30
申请号：US11537401
申请日：2006-09-29
申请人： Aaron John Nygren , Thomas Hein
发明人： Aaron John Nygren , Thomas Hein
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1004 , G11C11/4096 , G11C2029/0411
摘要： The present invention relates to a method of operating an electronic device and an electronic device. The electronic device comprises a signal path for transmitting data, an input/output interface connected with the signal path, a masking circuit and an error calculation circuit. The masking circuit is connected with the signal path and the error calculation circuit. The error calculation circuit is connected with the signal path. The signal path is connected with the masking circuit to deliver masking information to the masking circuit. The masking circuit considers the received masking information for masking the data and delivers the masked and non-masked data to the error detection circuit.
摘要翻译：本发明涉及操作电子设备和电子设备的方法。电子装置包括用于发送数据的信号路径，与信号路径连接的输入/输出接口，屏蔽电路和误差计算电路。掩蔽电路与信号路径和误差计算电路连接。误差计算电路与信号路径相连。信号路径与屏蔽电路连接，以将屏蔽信息传送到屏蔽电路。掩蔽电路考虑接收到的掩蔽信息以掩蔽数据，并将掩蔽和非掩蔽数据传送到错误检测电路。

3. 发明授权

US07802166B2 Memory controller, memory circuit and memory system with a memory controller and a memory circuit 有权
标题翻译：存储器控制器，存储器电路和具有存储器控制器和存储器电路的存储器系统
公开(公告)号：US07802166B2
公开(公告)日：2010-09-21
申请号：US11535961
申请日：2006-09-27
申请人： Aaron John Nygren , Thomas Hein , Martin Maier , Otto Schumacher
发明人： Aaron John Nygren , Thomas Hein , Martin Maier , Otto Schumacher
IPC分类号： H03M13/00
CPC分类号： G06F13/1668 , G06F11/1004
摘要： Methods and apparatus for adjusting a phase difference between clock signals. A first clock signal at a memory controller is adjusted relative to a clock second signal at a memory device. In one embodiment, data is transferred to the memory device according to the first clock signal, which has a predetermined phase relationship with second clock signal. Data received at the memory device is sampled at the memory device according to the second clock signal. Analysis is done of the data on the memory controller and of the received data on the memory circuit. On the basis of the analysis, an adjustment may be made to the phase relationship.
摘要翻译：用于调整时钟信号之间的相位差的方法和装置。存储器控制器处的第一时钟信号相对于存储器件处的时钟第二信号进行调整。在一个实施例中，根据与第二时钟信号具有预定相位关系的第一时钟信号将数据传送到存储器件。根据第二时钟信号，在存储器件处接收到的数据在存储器件中被采样。对存储器控制器上的数据和存储器电路上的接收数据进行分析。在分析的基础上，可以对相位关系进行调整。

4. 发明申请

US20080112255A1 TRAINING OF SIGNAL TRANSFER CHANNELS BETWEEN MEMORY CONTROLLER AND MEMORY DEVICE 审中-公开
标题翻译：记忆控制器与存储器件之间信号传输通道的训练
公开(公告)号：US20080112255A1
公开(公告)日：2008-05-15
申请号：US11560302
申请日：2006-11-15
申请人： Aaron John Nygren , Thomas Hein , Rex Kho
发明人： Aaron John Nygren , Thomas Hein , Rex Kho
IPC分类号： G11C8/00
CPC分类号： G11C29/02 , G11C5/04 , G11C29/025 , G11C29/50012
摘要： Apparatus and method of training a data transfer channel between a memory controller and a memory device connected to each other via a data signal transfer channel and an address signal transfer channel. The method comprises reading test data from a latching circuit connected to both an address signal input and a data or control signal output of the memory device or from a read only memory in the memory device, transferring a read signal representing the test data via the data signal transfer channel, detecting data from the read signal with a delay relative to a read clock signal; repeating the transferring, detecting steps, each time detecting the data at a different value of the delay; selecting a value of the delay, preferably a value at which the detected data equal the test data; and setting the delay to the selected value.
摘要翻译：通过数据信号传送通道和地址信号传送通道在存储器控制器和连接到彼此的存储器件之间训练数据传送通道的装置和方法。该方法包括从连接到存储器件的地址信号输入和数据或控制信号输出的存储电路或从存储器件中的只读存储器读取测试数据，经由数据传送表示测试数据的读取信号信号传输通道，相对于读取时钟信号以相对于读取时钟信号的延迟来检测来自读取信号的数据; 每次以不同的延迟值检测数据，重复传送，检测步骤; 选择延迟的值，优选地是检测数据等于测试数据的值; 并将延迟设置为所选值。

5. 发明授权

US07024326B2 Method of optimizing the timing between signals 失效
标题翻译：优化信号间定时的方法
公开(公告)号：US07024326B2
公开(公告)日：2006-04-04
申请号：US10835393
申请日：2004-04-30
申请人： Aaron John Nygren
发明人： Aaron John Nygren
IPC分类号： G01R35/00
CPC分类号： H03K5/135 , H03K2005/00084 , H03K2005/00104
摘要： A method of optimizing the timing between signals to be latched and a respective latching clock signal is suggested wherein test timings are provided according to which a delay test value of a clock delay line (CDL) are generated. According to the delay test values a clock signal (C) and a sample signal (S) are received through said clock delay line (CDL) and through said sample signal line (SSL), respectively. Respective phase differences for the distinct delay test values are obtained. A delay value is chosen and set for operation for which the respective obtained phase difference fits best to given target timing data.
摘要翻译：提出了一种优化要锁存的信号之间的定时和相应的锁存时钟信号的方法，其中提供了测试定时，根据该定时产生时钟延迟线（CDL）的延迟测试值。根据延迟测试值，通过所述时钟延迟线（CDL）和所述采样信号线（SSL）分别接收时钟信号（C）和采样信号（S）。获得不同延迟测试值的相位差。选择延迟值并设置用于各自获得的相位差最适合给定的目标定时数据的操作。

6. 发明授权

US08909998B2 Phase shift adjusting method and circuit 有权
标题翻译：相移调整方法和电路
公开(公告)号：US08909998B2
公开(公告)日：2014-12-09
申请号：US12946637
申请日：2010-11-15
申请人： Otto Schumacher , Martin Maier , Thomas Hein , Aaron John Nygren
发明人： Otto Schumacher , Martin Maier , Thomas Hein , Aaron John Nygren
IPC分类号： H03M13/33 , H04L7/02 , H04L7/04 , G01R31/317 , G06F11/07 , G06F1/10 , G06F11/18 , G01R31/3193 , G06F11/10 , G06F11/263 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/50 , H04L7/00
CPC分类号： H04L7/048 , G01R31/31725 , G01R31/31937 , G06F1/10 , G06F11/073 , G06F11/1004 , G06F11/18 , G06F11/186 , G06F11/263 , G11C7/1078 , G11C7/1084 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/023 , G11C29/025 , G11C29/028 , G11C29/50012 , G11C2207/2254 , H03M13/33 , H04L7/0008 , H04L7/0037 , H04L7/0091
摘要： Method and system of adjusting a first phase shift between a first data signal and a clock signal at a sending device. First and second test signals representing first and second test data, respectively, are transmitted to a receiving device. The test signals have respective phase shifts relative to the clock signal. An error detection code is calculated from first and second received data carried by the transmitted signals. The error detection code is transmitted from the receiving device to the sending device. An estimated first received data is calculated from the error detection code, wherein the estimated first received data are calculated under the assumption that the second received data are identical to the second test data. The first phase shift is adjusted on the basis of a comparison of the estimated first received data and the first test data.
摘要翻译：在发送设备处调整第一数据信号和时钟信号之间的第一相移的方法和系统。分别表示第一和第二测试数据的第一和第二测试信号被发送到接收设备。测试信号相对于时钟信号具有相应的相移。由发送的信号承载的第一和第二接收数据计算错误检测码。错误检测码从接收设备发送到发送设备。从错误检测码计算估计的第一接收数据，其中在第二接收数据与第二测试数据相同的假设下计算估计的第一接收数据。基于估计的第一接收数据和第一测试数据的比较来调整第一相移。

7. 发明申请

US20110185256A1 Adjustment of Write Timing Based on Error Detection Techniques 有权
标题翻译：基于错误检测技术调整写入时序
公开(公告)号：US20110185256A1
公开(公告)日：2011-07-28
申请号：US12846958
申请日：2010-07-30
申请人： Aaron John Nygren , Ming-Ju Edward Lee , Shadi M. Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger
发明人： Aaron John Nygren , Ming-Ju Edward Lee , Shadi M. Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger
IPC分类号： G06F11/08
CPC分类号： G06F13/4243
摘要： A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于基于错误检测功能的结果来调整存储器件中的写入定时。例如，该方法可以包括基于错误检测功能的结果来确定数据总线上的信号与写入时钟信号之间的写时序窗口。该方法还可以包括基于写时序窗口来调整数据总线上的信号与写入时钟信号之间的相位差。存储器件可以基于调整后的相位差来恢复数据总线上的数据。

8. 发明申请

US20100329045A1 Adjustment of Write Timing in a Memory Device 有权
标题翻译：调整存储器件中的写入时序
公开(公告)号：US20100329045A1
公开(公告)日：2010-12-30
申请号：US12490454
申请日：2009-06-24
申请人： Ming-Ju Edward LEE , Shadi M. Barakat , Warren Fritz Kruger , Xiaoling Xu , Toan Duc Pham , Aaron John Nygren
发明人： Ming-Ju Edward LEE , Shadi M. Barakat , Warren Fritz Kruger , Xiaoling Xu , Toan Duc Pham , Aaron John Nygren
IPC分类号： G11C7/00 , G11C8/00 , H04L7/00
CPC分类号： G11C7/22 , G06F13/1689 , G06F13/4234 , G11C7/222 , G11C11/4076
摘要： A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.
摘要翻译：提供了一种用于调整存储器件中的写时序的方法和系统。例如，该方法可以包括接收数据信号，写时钟信号和参考信号。该方法还可以包括随时间检测参考信号中的相移。参考信号的相移可用于调整数据信号和写入时钟信号之间的相位差，其中存储器件基于数据信号和写入时钟信号的调整的写入定时从数据信号中恢复数据。

9. 发明授权

US07411862B2 Control signal training 有权
标题翻译：控制信号训练
公开(公告)号：US07411862B2
公开(公告)日：2008-08-12
申请号：US11560293
申请日：2006-11-15
申请人： Thomas Hein , Aaron John Nygren , Rex Kho
发明人： Thomas Hein , Aaron John Nygren , Rex Kho
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G11C7/22 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： A control signal training system in an integrated circuit comprises a signal transmitting unit, the signal transmitting unit outputting control signals and sampling clock signals, the control signals and the sampling clock signals having a predetermined time phase with respect to each other, a signal receiving unit, the signal receiving unit latching control signals in relation to the sampling clock signals, and an evaluation unit connected to a reading unit and the signal transmitting unit, the evaluation unit determining concordance of the control signals outputted by the signal transmitting unit and the control signals read out by the reading unit from the signal receiving unit, the evaluation unit adapting the time phase between the control signals and the sampling clock signals step-by-step until concordance of the control signals outputted by the signal transmitting unit and the control signals read out the reading unit from the signal receiving unit is determined by the evaluation unit.
摘要翻译：集成电路中的控制信号训练系统包括信号发送单元，信号发送单元输出控制信号和采样时钟信号，控制信号和采样时钟信号相对于彼此具有预定的时间相位;信号接收单元信号接收单元相对于采样时钟信号锁存控制信号，以及连接到读取单元和信号发送单元的评估单元，评估单元确定由信号发送单元输出的控制信号和控制信号的一致性由读取单元从信号接收单元读出，评估单元逐步调整控制信号与采样时钟信号之间的时间相位，直到由信号发送单元输出的控制信号和读取的控制信号的一致从信号接收单元输出读取单元由评估确定单位。

10. 发明申请

US20080082898A1 ELECTRONIC DEVICE, METHOD FOR OPERATING AN ELECTRONIC DEVICE, MEMORY CIRCUIT AND METHOD OF OPERATING A MEMORY CIRCUIT 有权
标题翻译：电子设备，用于操作电子设备的方法，存储器电路和操作存储器电路的方法
公开(公告)号：US20080082898A1
公开(公告)日：2008-04-03
申请号：US11537401
申请日：2006-09-29
申请人： Aaron John Nygren , Thomas Hein
发明人： Aaron John Nygren , Thomas Hein
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1004 , G11C11/4096 , G11C2029/0411
摘要： The present invention relates to a method of operating an electronic device and an electronic device. The electronic device comprises a signal path for transmitting data, an input/output interface connected with the signal path, a masking circuit and an error calculation circuit. The masking circuit is connected with the signal path and the error calculation circuit. The error calculation circuit is connected with the signal path. The signal path is connected with the masking circuit to deliver masking information to the masking circuit. The masking circuit considers the received masking information for masking the data and delivers the masked and non-masked data to the error detection circuit.
摘要翻译：本发明涉及操作电子设备和电子设备的方法。电子装置包括用于发送数据的信号路径，与信号路径连接的输入/输出接口，屏蔽电路和误差计算电路。掩蔽电路与信号路径和误差计算电路连接。误差计算电路与信号路径相连。信号路径与屏蔽电路连接，以将屏蔽信息传送到屏蔽电路。掩蔽电路考虑接收到的掩蔽信息以掩蔽数据，并将掩蔽和非掩蔽数据传送到错误检测电路。

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