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    • 2. 发明授权
    • Java hardware accelerator using microcode engine
    • Java硬件加速器使用微码引擎
    • US07225436B1
    • 2007-05-29
    • US09687777
    • 2000-10-13
    • Mukesh K. Patel
    • Mukesh K. Patel
    • G06F9/45G06F9/44G06F15/00
    • G06F9/30174G06F9/3879G06F9/45516
    • A hardware Java™ accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level parallelism while the microcode stage allows the conversion of a single Java™ bytecode into multiple native instructions. A reissue buffer is provided which stores the converted instructions and reissues them when the system returns from an interrupt. In this manner, the hardware accelerator need not be flushed upon an interrupt A native PC monitor is also used. While the native PC is within a specific range, the hardware accelerator is enabled to convert the Java™ bytecodes into native instructions. When the native PC is outside the range, the hardware accelerator is disabled and the CPU operates on native instructions obtained from the memory.
    • 硬件Java TM加速器由解码级和微代码级组成。 分解为解码和微码级允许解码级实现指令级并行性,而微码级允许将单个Java TM字节码转换为多个本地指令。 提供重发缓冲器,其存储转换的指令,并且当系统从中断返回时重新发行它们。 以这种方式,硬件加速器不需要在中断时刷新。本机PC监视器也被使用。 当本机PC在特定范围内时,硬件加速器能够将Java(TM)字节码转换为本地指令。 当本地PC超出该范围时,硬件加速器被禁用,并且CPU对从存储器获得的本地指令进行操作。
    • 5. 发明授权
    • Method and system for verifying a traffic violation image
    • 用于验证交通违规图像的方法和系统
    • US07528741B2
    • 2009-05-05
    • US10598121
    • 2005-02-18
    • Rudiger Heinz Gebert
    • Rudiger Heinz Gebert
    • G08G1/017
    • G08G1/054
    • A method 10 of verifying a traffic violation image and includes the step of automatically sensing 12 whether or not a vehicle commits a traffic violation, the step of automatically capturing 14 an image which shows a vehicle committing a traffic violation if it is sensed 12 that the vehicle has committed a traffic violation, the step of obtaining 16 verification data which verifies that the step of sensing 12 is accurate within acceptable limits, and the step of automatically combining 18 the obtained verification data with the captured traffic violation image to provide proof of the accurate sensing of the traffic violation. Also provided is an associated system.
    • 一种验证交通违规图像的方法10,并且包括自动感测12车辆是否犯有交通违规的步骤,如果感测到车辆违反,则自动捕获14表示车辆执行交通违规的图像的步骤12, 车辆已经犯了交通违规,获得16个验证数据的步骤,该验证数据验证感测12的步骤是否准确地在可接受的范围内,以及将获得的验证数据与捕获的交通违规图像自动组合18的步骤,以提供证明 准确感知交通违规。 还提供了相关联的系统。
    • 8. 发明授权
    • Weight sensor
    • 重量传感器
    • US07153383B2
    • 2006-12-26
    • US10450635
    • 2001-12-13
    • Rudiger Heinz Gebert
    • Rudiger Heinz Gebert
    • G01L1/00G01B13/00H01H3/00B32B37/02
    • G01G19/024G01G7/06Y10T29/49007Y10T156/1062Y10T156/1309Y10T156/1322
    • The invention provides a weight sensor (10) which includes a first electrically conductive sheet (12) electrically isolated from a second electrically conductive sheet (14) by inserts of a closed cell foamed polymeric dielectric (16) and an elastic dielectric (18) in spaces (20) formed between the inserts (16) located between the sheets (12, 14). The sensor (10) also includes capacitive measuring means (24), electrically connected between the first sheet (12) and the second sheet (14), which measures a change of capacitance between the sheets (12, 14) when a vehicle passes over the sheets (12, 14). The sensor (10) further includes converting means (26) for converting the change of capacitance to a number related to a weight of the vehicle.
    • 本发明提供了一种重量传感器(10),其包括通过闭孔发泡聚合物电介质(16)和弹性电介质(18)的插入物与第二导电片(14)电隔离的第一导电片(12) 形成在位于片材(12,14)之间的插入件(16)之间的空间(20)。 传感器(10)还包括电连接在第一片(12)和第二片(14)之间的电容测量装置(24),其测量当车辆经过时片材(12,14)之间的电容变化 片材(12,14)。 传感器(10)还包括转换装置(26),用于将电容变化转换为与车辆重量有关的数字。
    • 10. 发明授权
    • Memory circuit with crossover zones of reduced line width conductors
    • 具有减少线宽导线的交叉区的存储电路
    • US08369135B1
    • 2013-02-05
    • US12960416
    • 2010-12-03
    • Krishnakumar Mani
    • Krishnakumar Mani
    • G11C11/00
    • G11C5/063G11C11/1659H01L27/222
    • A memory circuit comprising a set of longitudinal conducting lines and a set of transverse conducting lines, wherein, each conducting line comprises alternating regions of reduced and increased line widths. The set of transverse conducting lines overlies the set of longitudinal conducting lines to define crossover zones wherein the reduced line width regions of the transverse conducting lines cross over the reduced line width regions of the longitudinal conducting lines. The circuit further comprises addressable magnetic storage elements, each disposed within a crossover zone between a longitudinal conducting line and a transverse conducting line thereof. The reduced line width regions improve magnetic flux efficiency in the magnetic storage elements and the increased line width regions lower the resistance in the conducting lines.
    • 一种存储电路,包括一组纵向导线和一组横向导线,其中每条导线包括线宽减小和增加的交替区域。 横向导线的一组覆盖在该组纵向导线上以限定交叉区域,其中横向导线的减小的线宽度区域横穿纵向导线的减小的线宽度区域。 电路还包括可寻址的磁存储元件,每个磁性存储元件设置在纵向导线与其横向导线之间的交叉区域内。 减小的线宽度区域改善磁存储元件中的磁通效率,并且增加的线宽度区域降低导线中的电阻。