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    • 1. 发明授权
    • Semiconductor device with improved overlay margin and method of manufacturing the same
    • 具有改善覆盖边界的半导体器件及其制造方法
    • US07414279B2
    • 2008-08-19
    • US11049428
    • 2005-02-02
    • Joon-Soo Park
    • Joon-Soo Park
    • H01L27/108
    • H01L27/10885H01L27/10814H01L27/10876H01L27/10888
    • Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line that extends at a right angle to the bit line across the active region and is electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line can be integrally formed.
    • 提供了具有改进的覆盖边缘的半导体器件及其制造方法。 一方面,一种方法包括在衬底中形成掩埋位线; 在所述衬底中形成隔离层以限定有源区,所述隔离层平行于所述位线而不重叠所述位线; 以及通过在所述有源区中形成所述栅极图案形成包括栅极图案和导电线的栅极线,并且形成在所述有源区域上与所述位线成直角延伸的导电线,并且电连接到所述栅极图案 在那里 栅极图案和导线可以一体形成。