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1. 发明授权

US09599658B2 Method and apparatus for signaling partial shadowing of a photovoltaic generator 有权
公开(公告)号：US09599658B2
公开(公告)日：2017-03-21
申请号：US14499585
申请日：2014-09-29
申请人： SMA Solar Technology AG
发明人： Christopher Merz , Sebastian Bieniek , Markus Hopf , Felix Eger
IPC分类号： H02S50/10 , G01R31/26 , H01L31/02
CPC分类号： G01R31/2607 , H01L31/02021 , H02S50/10 , Y02E10/50
摘要： The disclosure relates to a method for signaling partial shadowing within a PV generator including at least two partial PV generators connected in parallel. The method includes performing a reference impedance measurement on each of the at least two partial PV generators in a state of uniform irradiation of the PV generator, and determining at least one reference resonant property of each of the at least two partial PV generators from the reference impedance measurement. Furthermore, impedance measurements are carried out on the at least two partial PV generators at a first operating point of the PV generator during operation of the PV generator. Resonant properties of the partial PV generators are determined from the impedance measurements. Partial shadowing within the PV generator is detected and signaled if a difference between the resonant properties of the partial PV generators at the first operating point differs from a difference between the reference resonant properties of the partial PV generators. The disclosure also relates to an apparatus suitable for carrying out the method.

2. 发明授权

US09577077B2 Well controlled conductive dot size in flash memory 有权
标题翻译：闪存中控制良好的导电点尺寸
公开(公告)号：US09577077B2
公开(公告)日：2017-02-21
申请号：US14308808
申请日：2014-06-19
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Tsu-Hui Su , Chih-Ming Chen , Szu-Yu Wang , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L27/115 , H01L29/66 , H01L29/792 , H01L21/28 , H01L29/423 , H01L29/788
CPC分类号： H01L29/66833 , H01L21/28273 , H01L21/28282 , H01L29/42324 , H01L29/4234 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a first tunnel oxide is formed over a semiconductor substrate. A self-assembled monolayer (SAM) is then formed on the first tunnel oxide. The SAM includes spherical or spherical-like crystalline silicon dots having respective diameters which are less than approximately 30 nm. A second tunnel oxide is then formed over the SAM.
摘要翻译：本公开的一些实施例涉及用于形成快闪存储器的方法。在该方法中，在半导体衬底上形成第一隧道氧化物。然后在第一隧道氧化物上形成自组装单层（SAM）。 SAM包括具有小于约30nm的相应直径的球形或球形晶体硅点。然后在SAM上形成第二隧道氧化物。

3. 发明授权

US09571242B2 Methods and devices for mitigating interference 有权
标题翻译：减轻干扰的方法和装置
公开(公告)号：US09571242B2
公开(公告)日：2017-02-14
申请号：US13871079
申请日：2013-04-26
申请人： Intel Mobile Communications GmbH
发明人： Rajarajan Balraj
IPC分类号： H04L5/00 , H04W24/02 , H04J11/00 , H04L27/26
CPC分类号： H04L5/0032 , H04J11/005 , H04L5/005 , H04L27/2613 , H04W24/02
摘要： A method includes receiving a signal including a two-dimensional signal pattern in a time-frequency representation, wherein the two-dimensional signal pattern includes a first reference signal at a predetermined first position in the two-dimensional signal pattern and at least one second reference signal at a predetermined second position in the two-dimensional signal pattern. The first reference signal includes cell identification information of a target cell of a cellular radio system and the at least one second reference signal includes cell identification information of at least one interfering cell of the cellular radio system. The method further includes determining a first noise covariance measure based on the first reference signal, determining at least one second noise covariance measure based on the at least one second reference signal, and mitigating an interference included in the received signal based on the first noise covariance measure and the at least one second noise covariance measure.
摘要翻译：一种方法包括在时间频率表示中接收包括二维信号模式的信号，其中二维信号模式包括在二维信号模式中的预定第一位置的第一参考信号和至少一个第二参考信号在二维信号图案中的预定的第二位置。第一参考信号包括蜂窝无线电系统的目标小区的小区识别信息，并且至少一个第二参考信号包括蜂窝无线电系统的至少一个干扰小区的小区标识信息。该方法还包括基于第一参考信号来确定第一噪声协方差度量，基于至少一个第二参考信号确定至少一个第二噪声协方差度量，以及基于第一噪声协方差来减轻包含在接收信号中的干扰测量和至少一个第二噪声协方差度量。

4. 发明授权

US09569384B2 Conditional links for direct memory access controllers 有权
标题翻译：直接内存访问控制器的条件链接
公开(公告)号：US09569384B2
公开(公告)日：2017-02-14
申请号：US13803811
申请日：2013-03-14
申请人： Infineon Technologies AG
发明人： Frank Hellwig , Simon Cottam , Harald Zweck
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a bus controller having a system bus interface and configured to read a pattern from a memory location via the system bus interface. Pattern comparison logic compares the read pattern to at least one predetermined pattern. Control logic induces the bus controller to process a first conditional link over the system bus interface if the read pattern differs from the predetermined pattern, and induces the bus controller to process a second conditional link over the system bus interface if the read pattern differs from the predetermined pattern.
摘要翻译：一些实施例涉及直接存储器访问（DMA）控制器。 DMA控制器包括具有系统总线接口并被配置为经由系统总线接口从存储器位置读取模式的总线控制器。图案比较逻辑将读取图案与至少一个预定图案进行比较。如果读取模式与预定模式不同，则控制逻辑引起总线控制器处理系统总线接口上的第一条件链路，并且如果读取模式与系统总线接口不同，则总线控制器通过系统总线接口处理第二条件链路预定模式。

5. 发明授权

US09567204B2 Microelectrochemical systems (MEMS) device having a seal layer arranged over or lining a hole in fluid communication with a cavity of the MEMS device 有权
标题翻译：具有密封层的微电化学系统（MEMS）装置，该密封层布置在与MEMS装置的空腔流体连通的孔中或衬里
公开(公告)号：US09567204B2
公开(公告)日：2017-02-14
申请号：US14472636
申请日：2014-08-29
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chia-Ming Hung , Shao-Chi Yu , Hsiang-Fu Chen , Wen-Chuan Tai , Hsin-Ting Huang
IPC分类号： B81B7/00 , B81C1/00
CPC分类号： B81C1/00238 , B81B7/0038 , B81B7/0061 , B81B2201/0264 , B81B2203/0315 , B81C2203/0136 , B81C2203/0145 , B81C2203/019 , B81C2203/036
摘要： A method for manufacturing a microelectromechanical systems (MEMS) device is provided. According to the method, a semiconductor structure is provided. The semiconductor structure includes an integrated circuit (IC) substrate, a dielectric layer arranged over the IC substrate, and a MEMS substrate arranged over the IC substrate and the dielectric layer to define a cavity between the MEMS substrate and the IC substrate. The MEMS substrate includes a MEMS hole in fluid communication with the cavity and extending through the MEMS substrate. A sealing layer is formed over or lining the MEMS hole to hermetically seal the cavity with a reference pressure while the semiconductor structure is arranged within a vacuum having the reference pressure. The semiconductor structure resulting from application of the method is also provided.
摘要翻译：提供了一种用于制造微机电系统（MEMS）装置的方法。根据该方法，提供半导体结构。半导体结构包括集成电路（IC）衬底，布置在IC衬底上的电介质层和布置在IC衬底和电介质层上的MEMS衬底，以在MEMS衬底和IC衬底之间限定空腔。 MEMS衬底包括与空腔流体连通并延伸穿过MEMS衬底的MEMS孔。在半导体结构布置在具有参考压力的真空中之前，密封层形成在MEMS孔的上方或衬套上，以密封空腔与参考压力。还提供了由应用该方法得到的半导体结构。

6. 发明授权

US09559614B2 Grid-connected inverter, inverter arrangement and method for operating an inverter arrangement 有权
标题翻译：并网逆变器，变频器布置及运行变频器装置的方法
公开(公告)号：US09559614B2
公开(公告)日：2017-01-31
申请号：US14025944
申请日：2013-09-13
申请人： SMA Solar Technology AG
发明人： Thomas Eberhardt , Josef Petschenka , Christopher Krause , Christian Landau
IPC分类号： H02M7/5387 , H02J3/38 , H02M7/493
CPC分类号： H02M7/53873 , H02J3/383 , H02M7/493 , Y02E10/563 , Y10T307/707
摘要： A grid-connected inverter for feeding current via a transformer into an electric power grid includes an output bridge arrangement that is actuated via a pulse width modulator, wherein a periodic auxiliary signal is used to determine switching times of the output bridge arrangement. The inverter also includes a synchronization unit for phase synchronization of the auxiliary signal with the electric power grid, wherein the synchronization unit is configured to set a predetermined phase offset (ΔΦ0) of the periodic auxiliary signal with respect to a phase of the electric power grid.
摘要翻译：用于经由变压器将电流馈送到电力网的并网逆变器包括通过脉宽调制器致动的输出桥式装置，其中使用周期性辅助信号来确定输出桥式装置的开关时间。逆变器还包括用于辅助信号与电网相位同步的同步单元，其中同步单元被配置为相对于电力网的相位来设置周期性辅助信号的预定相位偏移（ΔΦ0）。

7. 发明授权

US09559294B2 Self-aligned magnetoresistive random-access memory (MRAM) structure for process damage minimization 有权
标题翻译：自对准磁阻随机存取存储器（MRAM）结构，用于过程损坏最小化
公开(公告)号：US09559294B2
公开(公告)日：2017-01-31
申请号：US14608313
申请日：2015-01-29
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chern-Yow Hsu , Shih-Chang Liu
IPC分类号： H01L21/00 , H01L29/82 , H01L43/08 , H01L43/02 , H01L43/12 , H01L27/22
CPC分类号： H01L43/08 , H01L27/222 , H01L27/228 , H01L43/02 , H01L43/12
摘要： A magnetoresistive random-access memory (MRAM) cell with a dual sidewall spacer structure is provided. The MRAM cell includes an anti-ferromagnetic layer, a pin layer, a free layer, a first sidewall spacer layer, and a second sidewall spacer layer. The pin layer is arranged over the anti-ferromagnetic layer and has a fixed magnetic polarity. The free layer is arranged over the pin layer and has a variable magnetic polarity. The first sidewall spacer layer extends from over the pin layer along sidewalls of the free layer. The second sidewall spacer layer extends from over the anti-ferromagnetic layer along sidewalls of the pin layer and the first sidewall spacer layer. A method for manufacturing the MRAM cell is also provided.
摘要翻译：提供具有双重侧壁间隔结构的磁阻随机存取存储器（MRAM）单元。 MRAM单元包括反铁磁层，引脚层，自由层，第一侧壁间隔层和第二侧壁间隔层。引脚层布置在反铁磁层上并具有固定的磁极性。自由层布置在引脚层上并具有可变的磁极性。第一侧壁间隔层沿自由层的侧壁从引脚层的上方延伸。第二侧壁间隔层沿着反铁磁层从针层和第一侧壁间隔层的侧壁延伸。还提供了制造MRAM单元的方法。

8. 发明授权

US09558914B2 Bipolar wafer charge monitor system and ion implantation system comprising same 有权
标题翻译：双极晶片电荷监测系统和包括其的离子注入系统
公开(公告)号：US09558914B2
公开(公告)日：2017-01-31
申请号：US14631066
申请日：2015-02-25
申请人： Axcelis Technologies, Inc.
发明人： Marvin Farley , Takao Sakase , Joseph Foley
IPC分类号： H01J37/08 , H01J37/304 , H01J37/317 , H01J37/32
CPC分类号： H01J37/304 , H01J37/3171 , H01J37/32412 , H01J2237/0041 , H01J2237/0203 , H01J2237/24507 , H01J2237/304 , H01J2237/31701 , H01L22/14
摘要： A charge monitor having a Langmuir probe is provided, wherein a positive and negative charge rectifier are operably coupled to the probe and configured to pass only a positive and negative charges therethrough, respectively. A positive current integrator is operably coupled to the positive charge rectifier, wherein the positive current integrator is biased via a positive threshold voltage, and wherein the positive current integrator is configured to output a positive dosage based, at least in part, on the positive threshold voltage. A negative current integrator is operably coupled to the negative charge rectifier, wherein the negative current integrator is biased via a negative threshold voltage, and wherein the negative current integrator is configured to output a negative dosage based, at least in part, on the negative threshold voltage. A positive charge counter and a negative charge counter are configured to respectively receive the output from the positive current integrator and negative current integrator in order to provide a respective cumulative positive charge value and cumulative negative charge value associated with the respective positive charge and negative charge.
摘要翻译：提供具有朗缪尔探针的电荷监测器，其中正和负电荷整流器可操作地耦合到探针并且被配置为分别仅通过正和负电荷。正电流积分器可操作地耦合到正电荷整流器，其中正电流积分器经由正阈值电压偏置，并且其中正电流积分器被配置为至少部分地基于正阈值输出正剂量电压。负电流积分器可操作地耦合到负电荷整流器，其中负电流积分器经由负阈值电压被偏置，并且其中负电流积分器被配置为基于至少部分地基于负阈值输出负剂量电压。配置正电荷计数器和负电荷计数器以分别接收来自正电流积分器和负电流积分器的输出，以便提供与相应的正电荷和负电荷相关联的相应的累积正电荷值和累积负电荷值。

9. 发明授权

US09558797B2 Method and apparatus for controlling current in an array cell 有权
标题翻译：用于控制阵列单元中的电流的方法和装置
公开(公告)号：US09558797B2
公开(公告)日：2017-01-31
申请号：US15095482
申请日：2016-04-11
申请人： Infineon Technologies AG
发明人： Giacomo Curatolo , Wolf Allers
IPC分类号： G11C7/22 , G11C7/12 , G11C5/14 , G11C7/20
CPC分类号： G11C7/12 , G11C5/14 , G11C7/20
摘要： A method and an apparatus for controlling current in an array cell is disclosed. The method includes applying a supply voltage to a first access point of a transistor, precharging a second access point of the transistor to a predetermined voltage, applying a control voltage to a third access point of the transistor, and discharging the second access point of the transistor to turn on the transistor which causes a current flow through the array cell connected to the transistor.
摘要翻译：公开了一种用于控制阵列单元中的电流的方法和装置。该方法包括将电源电压施加到晶体管的第一接入点，将晶体管的第二接入点预先充电至预定电压，将控制电压施加到晶体管的第三接入点，以及将晶体管的第二接入点晶体管导通晶体管，其导致电流流过连接到晶体管的阵列单元。

10. 发明授权

US09551923B2 Cut mask design layers to provide compact cell height 有权
标题翻译：切割面膜设计层以提供紧凑的细胞高度
公开(公告)号：US09551923B2
公开(公告)日：2017-01-24
申请号：US14247409
申请日：2014-04-08
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yen-Sen Wang , Ming-Yi Lin , Chen-Hung Lu , Jyh-Kang Ting
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G03F1/00 , H01L27/0207 , H01L27/11807 , H01L2027/11874
摘要： Some embodiments relate to a method of designing an integrated circuit layout. In this method, a plurality of design shapes are provided on different design layers over an active area within a graphical representation of the layout. A connection extends perpendicularly between a first design shape formed on a first design layer and a second design shape formed on the first design layer. First and second cut mask shapes on first and second cut mask design layers, respectively, are generated. The first cut shape removes portions of the first design layer and the second cut shape removes portions of the second design layer.
摘要翻译：一些实施例涉及设计集成电路布局的方法。在该方法中，在布局的图形表示内的有效区域上，在不同的设计层上提供多个设计形状。连接在形成在第一设计层上的第一设计形状和形成在第一设计层上的第二设计形状之间垂直延伸。产生分别在第一和第二切割掩模设计层上的第一和第二切割掩模形状。第一切割形状去除第一设计层的部分，并且第二切割形状去除第二设计层的部分。

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