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1. 发明授权

US06967494B2 Wafer-interposer assembly 失效
标题翻译：晶圆插入器组件
公开(公告)号：US06967494B2
公开(公告)日：2005-11-22
申请号：US10772951
申请日：2004-02-05
申请人： Jerry D. Kline
发明人： Jerry D. Kline
IPC分类号： H01L23/498 , G01R31/28 , H01L21/66
CPC分类号： H01L23/49827 , B33Y70/00 , B33Y80/00 , H01L23/49805 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A wafer-interposer assembly (10) includes a semiconductor wafer (12) having a plurality of semiconductor die (14) that have a plurality of first electrical contact pads (16). An interposer (22) is connected to the semiconductor wafer (12) such that a plurality of second electrical contact pads (26) associated with the interposer (22) are respectively connected to at least some of the first electrical contact pads (16) via conductive attachment elements (20). A communication interface (28) is integrally associated with the interposer (22) and electrically connected to at least some of the plurality of second electrical contact pads (26). The interposer (22) and the semiconductor wafer (12) are operable to be singulated into a plurality of chip assemblies.
摘要翻译：晶片插入器组件（10）包括具有多个第一电接触焊盘（16）的多个半导体管芯（14）的半导体晶片（12）。插入器（22）连接到半导体晶片（12），使得与插入器（22）相关联的多个第二电接触焊盘（26）分别通过至少一些第一电接触焊盘（16）经由导电附接元件（20）。通信接口（28）与插入器（22）整体地相关联并且电连接到多个第二电接触焊盘（26）中的至少一些。插入器（22）和半导体晶片（12）可操作以被分成多个芯片组件。

2. 发明授权

US06963583B1 Generic call server and method of converting signaling protocols 有权
标题翻译：通用呼叫服务器和信令协议转换方法
公开(公告)号：US06963583B1
公开(公告)日：2005-11-08
申请号：US09676791
申请日：2000-09-29
申请人： George Foti
发明人： George Foti
IPC分类号： H04L29/06 , H04Q3/00 , H04J3/22 , H04J3/16
CPC分类号： H04L65/1043 , H04L29/06027 , H04L65/1006 , H04L69/08 , H04Q3/0025
摘要： A generic call server in a hybrid 2G/3G telecommunications network having a plurality of network components that utilize a plurality of different signaling protocols. The call server performs call-control functions and interfaces between any two network components selected from the plurality of components. A Generic Call-control State Machine (GCSM) performs call-control functions that are common to all of the protocols. A plurality of external signaling systems interface between the GCSM and the network components and perform call-control functions that are specific to each protocol. The generic call server may also include a Media Gateway (MGW) Handler that acts as a media signaling protocol handling server and interfaces between the GCSM and a media gateway.
摘要翻译：具有使用多个不同信令协议的多个网络组件的混合2G / 3G电信网络中的通用呼叫服务器。呼叫服务器执行从多个组件中选择的任何两个网络组件之间的呼叫控制功能和接口。通用呼叫控制状态机（GCSM）执行所有协议通用的呼叫控制功能。多个外部信令系统在GCSM和网络组件之间进行接口，并执行特定于每个协议的呼叫控制功能。通用呼叫服务器还可以包括用作媒体信令协议处理服务器的媒体网关（MGW）处理器，以及GCSM和媒体网关之间的接口。

3. 发明授权

US06952534B1 System and method for generating return-to-zero (RZ) optical data in a digital lightwave communications system 有权
标题翻译：用于在数字光波通信系统中产生归零（RZ）光数据的系统和方法
公开(公告)号：US06952534B1
公开(公告)日：2005-10-04
申请号：US09927754
申请日：2001-08-10
申请人： John K. Sikora
发明人： John K. Sikora
IPC分类号： G02F1/01 , H04B10/00
CPC分类号： G02F1/0123
摘要： A system and method for generating return-to-zero (RZ) optical data in a digital lightwave communications system using a two-stage modulator arrangement. RF electrical data is provided to a first stage modulator for modulating a light input into an intermediary optical data output having a non-return-to-zero (NRZ) format. Phase differences between the data and a clock signal associated therewith are controlled via a phase feedback control loop that is operable responsive to a phase dither reference signal. The clock signal is adjusted based on a phase control signal provided by the phase feedback control loop so as to generate a phase-adjusted clock. The phase-adjusted clock is supplied to a second stage modulator operable to blank out a suitable portion of each NRZ data bit interval and thereby create optical data having the RZ format.
摘要翻译：一种在使用两级调制器装置的数字光波通信系统中产生归零（RZ）光学数据的系统和方法。 RF电数据被提供给第一级调制器，用于将光输入调制成具有不归零（NRZ）格式的中间光数据输出。通过经相位抖动参考信号可操作的相位反馈控制回路来控制与数据相关的时钟信号之间的相位差。基于由相位反馈控制环路提供的相位控制信号来调整时钟信号，以产生相位调整时钟。相位调整的时钟被提供给第二级调制器，可操作以消除每个NRZ数据位间隔的合适部分，从而创建具有RZ格式的光学数据。

4. 发明授权

US06917612B2 System and method for address resolution in internet protocol (IP)-based networks 有权
标题翻译：基于互联网协议（IP）的网络中地址解析的系统和方法
公开(公告)号：US06917612B2
公开(公告)日：2005-07-12
申请号：US09852536
申请日：2001-05-11
申请人： George Foti , Sorin Surdila
发明人： George Foti , Sorin Surdila
IPC分类号： H04L29/06 , H04L29/12 , H04M7/00 , H04L12/66
CPC分类号： H04L61/1511 , H04L29/06 , H04L29/06027 , H04L29/12018 , H04L29/12066 , H04L29/1216 , H04L61/10 , H04L61/157 , H04L65/1006 , H04L65/1009 , H04L65/103 , H04L65/1043 , H04L65/1069 , H04M7/006
摘要： A system and unified method of address resolution in an IP-based network. A Resolver determines whether an input address is a URL/URI, and if so, extracts a domain name. If the input address is an E.164 number, the Resolver converts the E.164 number into a domain name in ENUM format. The Resolver then sends a domain name query to a DNS which, if able, returns the IP address for either a Global MGCF or a destination server along with a supported Application protocol. If the DNS is unable to perform the translation, or the Application protocol returned is not supported by the requesting application, the Resolver sends a domain name query to an extended Location Server (LS) to obtain an IP address of a gateway function capable of interfacing with the destination server.
摘要翻译：一种基于IP的网络中地址解析的系统和统一方法。解析器确定输入地址是否是URL / URI，如果是，则提取域名。如果输入地址是E.164号码，则Resolver将E.164号码转换为ENUM格式的域名。然后，Resolver将域名查询发送到DNS，如果可以，DNS返回全局MGCF或目标服务器的IP地址以及支持的应用协议。如果DNS无法执行翻译，或者请求应用程序不支持应用程序协议，则Resolver将一个域名查询发送到扩展位置服务器（LS），以获取能够进行接口的网关功能的IP地址与目标服务器。

5. 发明授权

US06886078B1 Simultaneous access and cache loading in a hierarchically organized memory circuit 有权
标题翻译：在分层组织的存储器电路中同时访问和缓存加载
公开(公告)号：US06886078B1
公开(公告)日：2005-04-26
申请号：US09886577
申请日：2001-06-21
申请人： Richard S. Roy
发明人： Richard S. Roy
IPC分类号： G06F12/08 , G11C7/22 , G06F12/00
CPC分类号： G06F12/0897 , G11C7/22 , G11C2207/2245
摘要： A hierarchically organized, compilable semiconductor memory circuit having multiple levels with simultaneous access and cache loading. A first level memory portion and at least a next level memory portion are provided as part of the semiconductor memory circuit, wherein the memory portions are associated with separate Data In (DIN) and Data Out (DOUT) buffer blocks for effectuating data operations. DIN buffer blocks of the first level and intermediate levels, if any, are provided with multiplexing circuitry that is selectively actuatable for providing data accessed in the next level memory portion to Local Data In (LDIN) driver circuitry, whereby the accessed data is simultaneously loaded into the first and intermediate levels. Accordingly, extra clock cycles are saved from cache loading of the data used for subsequent memory operations.
摘要翻译：具有层次组织的，可编译的半导体存储器电路，具有具有同时访问和高速缓存加载的多个级别。提供第一级存储器部分和至少下一级存储器部分作为半导体存储器电路的一部分，其中存储器部分与用于实现数据操作的单独的数据输入（DIN）和数据输出（DOUT）缓冲器块相关联。提供第一级和中级（如果有的话）的DIN缓冲器块，其具有可选择性地致动以将在下一级存储器部分中访问的数据提供给本地数据输入（LDIN）驱动器电路的多路复用电路，由此所访问的数据被同时加载进入第一和第二级。因此，从用于后续存储器操作的数据的高速缓存加载中节省额外的时钟周期。

6. 发明授权

US07251453B1 Mobile marine communications apparatus and method for use of same 有权
标题翻译：移动式海上通信装置及其使用方法
公开(公告)号：US07251453B1
公开(公告)日：2007-07-31
申请号：US11110566
申请日：2005-04-20
申请人： Kent David Newman , Todd William Crocker
发明人： Kent David Newman , Todd William Crocker
IPC分类号： H04B7/15
CPC分类号： H04B7/15
摘要： A marine radio wireless communication system (10) incorporating a remote wireless handset (26) and a fixed mount marine radio (18) for wireless communication on board a waterborne vessel (12) is disclosed. At least one marine radio remote wireless handset (26) is associated with and wirelessly linked to the fixed mount marine radio (18) for onboard remote acoustic communications between the two. Each fixed mount marine radio (18) and marine radio remote wireless handset (26) incorporates a speaker (80, 106) and a microphone (72, 102).
摘要翻译：公开了一种结合有远程无线手机（26）的海上无线电无线通信系统（10）和用于水上船只（12）上的无线通信的固定安装的海上无线电（18）。至少一个海洋无线电远程无线手机（26）与固定安装的海上无线电装置（18）相关联并与之无线连接，用于两者之间的车载远程声音通信。每个固定安装的海上无线电（18）和海洋无线电远程无线手机（26）包括扬声器（80,106）和麦克风（72,102）。

7. 发明授权

US07245830B2 Method and apparatus for scheduling transmission of data bursts in an optical burst switching network 失效
标题翻译：调度光突发交换网络中数据突发传输的方法和装置
公开(公告)号：US07245830B2
公开(公告)日：2007-07-17
申请号：US10418588
申请日：2003-04-17
申请人： Saravut Charcranoon , Tarek S. El-Bawab , Jong-Dug Shin , Hakki Candan Cankaya
发明人： Saravut Charcranoon , Tarek S. El-Bawab , Jong-Dug Shin , Hakki Candan Cankaya
IPC分类号： H04J14/00
CPC分类号： H04Q11/0066 , H04Q2011/0064 , H04Q2011/0084
摘要： Apparatus and method for scheduling transmission of data bursts in an OBS network are described. One embodiment is a router in an OBS network, the router comprising a grouper module for collecting a group of BHPs arriving during a BHP collecting period and classifying each BHP of the group of BHPs into corresponding baskets depending on the data channel scheduling window of its corresponding data burst; a classifier and channel assignment module for assigning data bursts to appropriate data channels; and a channel scheduler for constructing an interval graph representing data bursts corresponding to BHPs classified in a single one of the baskets having overlapping segments on each data channel as adjacent vertices and scheduling data bursts on each data channel based on a process that finds a maximum number of non-adjacent vertices on the interval graph.
摘要翻译：描述了用于调度OBS网络中数据突发传输的装置和方法。一个实施例是OBS网络中的路由器，路由器包括用于收集在BHP收集期间到达的一组BHP的分组器模块，并且根据其对应的数据信道调度窗口将BHP组中的每个BHP分类为对应的篮子数据突发分类器和信道分配模块，用于将数据突发分配给适当的数据信道; 以及频道调度器，用于构建间隔图，其表示与在每个数据信道上具有重叠片段的单个篮子中分类的BHP相对应的数据突发，作为相邻顶点，并且基于找到最大数量的处理来调度每个数据信道上的数据突发的间隔图上的非相邻顶点。

8. 发明授权

US07197438B1 System and method for memory compiler characterization 有权
标题翻译：用于内存编译器表征的系统和方法
公开(公告)号：US07197438B1
公开(公告)日：2007-03-27
申请号：US09981954
申请日：2001-10-18
申请人： Deepak Mehta , Andrew Knight , Deepak Sabharwal , Raymond Tak-Hoi
发明人： Deepak Mehta , Andrew Knight , Deepak Sabharwal , Raymond Tak-Hoi
IPC分类号： G06F17/10
CPC分类号： G06F17/505
摘要： A memory compiler characterization system and method for determining parametric data, wherein memory compilers of a first type are rigorously characterized and memory compilers of a second type are sparsely characterized with respect to a particular parameter. Absolute scale factors are determined based on the ratio of the parametric data points of two congruent memory compilers, one from each type. Interpolated scale factors are obtained based on the absolute scale factors. Parametric data for the remaining compilers of the sparsely characterized compiler set is filled out by applying the interpolated scale factors in conjunction with the data of the congruent memory compilers of the first type.
摘要翻译：一种用于确定参数数据的存储器编译器表征系统和方法，其中严格地表征第一类型的存储器编译器，并且关于特定参数稀疏地表征第二类型的存储器编译器。绝对比例因子是根据两个一致的存储器编译器的参数数据点的比例确定的，每个类型都是一个。基于绝对比例因子得到内插比例因子。稀疏表征的编译器集合的剩余编译器的参数数据通过将内插的比例因子结合第一类型的一致的存储器编译器的数据来填充。

9. 发明授权

US07171120B2 Optical switch controller for fair and effective lightpath reservation in an optical network 有权
标题翻译：光开关控制器，用于光网络中公平有效的光路预留
公开(公告)号：US07171120B2
公开(公告)日：2007-01-30
申请号：US10163962
申请日：2002-06-05
申请人： Timucin Ozugur , Dominique Verchere
发明人： Timucin Ozugur , Dominique Verchere
IPC分类号： H04B10/00
CPC分类号： H04Q11/0062 , H04L45/50 , H04L45/502 , H04L47/70 , H04L47/724 , H04L47/805 , H04L47/825 , H04L47/826 , H04Q11/0066 , H04Q2011/0039 , H04Q2011/0073 , H04Q2011/0077 , H04Q2011/0086 , H04Q2011/0088
摘要： An optical switch controller (“OSC”) and method for use in a Generalized Multi-Protocol Label Switching (“GMPLS”) network is described. A Used Pool (“UP”), an Available Pool (“AP”), and a Flagged Pool (“FP”) are maintained at the OSC. The FP includes wavelengths that have been suggested but not yet reserved by a lightpath. The UP includes wavelengths that are currently being used by LSPs. The AP includes wavelengths not included in the UP or the FP. Each wavelength included in the FP includes a time stamp. At each node along the path during lightpath establishment, for each wavelength of the Label Set, if the wavelength is an element of the node's UP, the wavelength is extracted from the Label Set. If the wavelength is an element of the node's FP, a determination is made whether the local clock time minus the time stamp for the wavelength is less than a first threshold. If so, the wavelength is extracted from the Label Set; otherwise, the wavelength is extracted from the Label Set and included in a Flagged Set. For each wavelength of the FP, upon expiration of the time stamp, the wavelength is returned to the AP.
摘要翻译：描述了在广义多协议标签交换（“GMPLS”）网络中使用的光开关控制器（“OSC”）和方法。在OSC中维护二手池（“UP”），可用池（“AP”）和标记池（“FP”）。 FP包括已被建议但尚未被光路保留的波长。 UP包括LSP正在使用的波长。 AP包括不包括在UP或FP中的波长。包括在FP中的每个波长包括时间戳。在光路建立期间沿路径的每个节点，对于标签集的每个波长，如果波长是节点的UP的元素，则从标签集中提取波长。如果波长是节点FP的元素，则确定本地时钟时间减去波长的时间戳是否小于第一阈值。如果是，则从标签集中提取波长; 否则，波长从标签集中提取并包含在标记集中。对于FP的每个波长，当时间戳结束时，波长被返回到AP。

10. 发明授权

US07114118B1 System and method for providing adjustable read margins in a semiconductor memory 有权
标题翻译：用于在半导体存储器中提供可调读取余量的系统和方法
公开(公告)号：US07114118B1
公开(公告)日：2006-09-26
申请号：US10216598
申请日：2002-08-09
申请人： Alex Shubat
发明人： Alex Shubat
IPC分类号： G11C29/30 , G11C29/20
CPC分类号： G11C29/026 , G11C16/04 , G11C29/02 , G11C29/028 , G11C29/24 , G11C29/50 , G11C29/50004
摘要： A system and method for effectuating a self-timed clock (STC) loop for memory access operations wherein an Embedded Test and Repair (ETR) processor engine is utilized for optimizing an access margin value. Upon compiling a semiconductor memory instance based on its configuration data, a default access margin value is passed to a wrapper interface associated with the memory instance. In one implementation, an adjusted access margin value is determined by an optimization algorithm operable to be executed on the ETR processor engine, which adjusted access margin value is used for generating the STC signal with a particular time setting that is optimized for a memory instance of a given size.
摘要翻译：一种用于实现用于存储器访问操作的自定时钟（STC）循环的系统和方法，其中使用嵌入式测试和修复（ETR）处理器引擎来优化访问余量值。在基于其配置数据编译半导体存储器实例时，将默认访问余量值传递到与存储器实例相关联的包装器接口。在一个实现中，经调整的访问边界值由可操作以在ETR处理器引擎上执行的优化算法确定，该调整的访问边界值用于生成具有针对存储器实例的存储器实例优化的特定时间设置的STC信号给定尺寸

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