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1. 发明公开

US20230163105A1 SEMICONDUCTOR CHIP STACK MODULE AND METHOD OF FABRICATING THE SAME 审中-公开
公开(公告)号：US20230163105A1
公开(公告)日：2023-05-25
申请号：US17533421
申请日：2021-11-23
申请人： Unity Power Technology Limited
发明人： Kuk Fong YIP
IPC分类号： H01L25/07 , H01L23/00 , H01L25/00
CPC分类号： H01L25/071 , H01L24/73 , H01L24/37 , H01L25/50 , H01L24/85 , H01L24/33 , H01L24/48 , H01L24/83 , H01L24/84 , H01L24/32 , H01L2224/3702 , H01L2224/33181 , H01L2224/73265 , H01L2224/32145 , H01L2224/32225 , H01L2224/48225 , H01L2224/73263
摘要： A semiconductor chip stack module that includes a substrate, two first semiconductor chips supported by the substrate, and a second semiconductor chip stacked on both of the two first semiconductor chips. The second semiconductor chip is electrically connected to both of the two first semiconductor chips by a conductive paste configured between the second semiconductor chip and both of the two first semiconductor chips. As multiple standard chips are stacked in the power module, and their number as well as the connection methods (e.g. series or parallel) are flexible so that the user can choose which electric characteristic(s) to be increased in the power module with the stacked chips.

2. 发明申请

US20230053874A1 SIC MOSFET WITH TRANSVERSE P+ REGION 有权
公开(公告)号：US20230053874A1
公开(公告)日：2023-02-23
申请号：US17405114
申请日：2021-08-18
申请人： Unity Power Technology Limited
发明人： Kuk Fong YIP
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66
摘要： A silicon carbide MOSFET device that includes a silicon carbide substrate of a first dopant type; a first silicon carbide layer of the first dopant type on top of the silicon carbide substrate; a second silicon carbide layer of a second dopant type embedded in a top portion of the first silicon carbide layer; a third silicon carbide layer of the first dopant type embedded in a top portion of the second silicon carbide layer; a gate oxide layer overlapped to the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer; and a fourth silicon carbide layer at least partially overlapping with the second silicon carbide layer along a direction normal to the silicon carbide substrate. The first silicon carbide layer has lower doping than the silicon carbide substrate and defines a drift region. The third silicon carbide layer has higher doping than the first silicon carbide layer. The third silicon carbide layer includes a plurality of third portions that run substantially along a first direction. The second silicon carbide layer includes a plurality of second portions that run substantially along the first direction. The fourth silicon carbide layer includes a plurality of fourth portions that run substantially along a second direction perpendicular to the first direction. The first and second directions each is parallel to the silicon carbide substrate. The transversely arranged P+ regions to N+ regions in some embodiments allow adequate P+ area to achieve good body diode performance and protection to the gate oxide, but without consuming significant area of the MOSFET cell.

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