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    • 1. 发明授权
    • Output circuit
    • 输出电路
    • US5694361A
    • 1997-12-02
    • US376089
    • 1995-01-20
    • Toshiya Uchida
    • Toshiya Uchida
    • G11C7/10H03K19/00H03K19/017G11C7/00
    • G11C7/106G11C7/1051H03K19/0016H03K19/01707
    • The turn-on time of an output transistor is minimized to suppress the average value of the load current, and the load is electrically charged with an intermediate potential prior to outputting data to suppress the instantaneous value of the load current. The output circuit holds the load in an open state when a predetermined reset signal has a first logic level, and drives the load from a high-potential side power source or a low-potential side power source depending on the logic level of the output data when said predetermined reset signal changes to a second logic level, wherein the timing at which the reset signal changes from the first logic to the second logic is delayed at least until the logic level of the output data has settled. Furthermore, the load is driven at an intermediate potential between the high-potential side power source voltage, and the low-potential side power source voltage and is then driven on the high-potential side power source or the low-potential side power source depending on the logic level of the output data.
    • 输出晶体管的导通时间被最小化以抑制负载电流的平均值,并且在输出数据之前负载以中间电位充电以抑制负载电流的瞬时值。 当预定的复位信号具有第一逻辑电平时,输出电路将负载保持在打开状态,并根据输出数据的逻辑电平从高电位侧电源或低电位侧电源驱动负载 当所述预定复位信号变为第二逻辑电平时,其中复位信号从第一逻辑变为第二逻辑的定时至少延迟至输出数据的逻辑电平已经稳定。 此外,负载被驱动在高电位侧电源电压和低电位侧电源电压之间的中间电位,然后在高电位侧电源或低电位侧电源上驱动依赖 在输出数据的逻辑电平上。