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    • 1. 发明授权
    • Electronic timepiece with controlled date display updating
    • 电子钟表控制日期显示更新
    • US06912181B2
    • 2005-06-28
    • US10371749
    • 2003-02-21
    • Akihiko MaruyamaAkihiro Sawada
    • Akihiko MaruyamaAkihiro Sawada
    • G04C9/00G04C10/04G04C17/00G04G19/12G04C3/00G04B1/00G04C23/00
    • G04C17/0066G04G19/12
    • An electronic timepiece without system failure at the time of transfer from the power-saving mode to the display mode is provided. A power-saving control circuit 400 controls drive of a date dial displaying a date when updating a date display, which has been stopped in a power-saving mode, to a current date at the time of transfer from the power-saving mode to the display mode. The power-saving control circuit 400 outputs a date dial drive inhibiting signal, which prohibits drive of the date dial 75, to a date-updating control circuit 300, if a voltage VDD of a power source unit B is less than or equal to a low threshold voltage V1. It outputs a date dial deceleration driving signal, which drives a date dial 75 with a predetermined speed slower than a normal update speed when transferring to the display mode, to a date-updating control circuit 300, if a source voltage VDD is equal to or less than a high threshold voltage V2.
    • 提供了在从省电模式转移到显示模式时没有系统故障的电子钟表。 省电控制电路400控制显示将在节电模式中已经停止的日期显示更新的日期的日期拨盘的驱动变换为从省电模式传送到当前日期的当前日期 显示模式。 如果电源单元B的电压VDD小于或等于1,则省电控制电路400输出禁止日期拨盘75的驱动的日期拨盘驱动禁止信号到日期更新控制电路300 低阈值电压V1。 如果源电压VDD等于或等于或者等于或者等于或者等于或者等于或者等于或者等于或者等于或者等于或者等于或者等于或者等于 小于高阈值电压V2。