会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 6. 发明授权
    • Redundancy circuit for memory
    • 内存冗余电路
    • US5504712A
    • 1996-04-02
    • US97598
    • 1993-07-23
    • Bertrand Conan
    • Bertrand Conan
    • G11C29/00
    • G11C29/80G11C29/846
    • Memories in integrated circuit form can have several amplifiers per data contact. To increase the possibilities of redundancy with a given number of redundancy columns without, causing too much space near the memory zone to be occupied by complicated multiplexers, the address AP used to select a single amplifier for each contact is used also to select one group of memories among several groups (as many groups as there are amplifiers per contact) in a defective address storage register. Only the defective addresses of this group are applied to a comparator used to detect whether a defective column address is received by the memory. A correlation is thus set up between the place where the defective column is located and the place where the redundancy column, which will be used to replace it, is located. This correlation results from the simultaneous selection by AP of a group of amplifiers and of a group of defective column addresses connected to these amplifiers.
    • 集成电路形式的存储器每个数据接口可以有多个放大器。 为了增加具有给定数量的冗余列的冗余的可能性,而不会在存储区附近造成太多的空间被复杂多路复用器占用,则用于为每个接点选择单个放大器的地址AP也用于选择一组 在有缺陷的地址存储寄存器中的几组之间的存储器(每个接点有放大器的组数很多)。 只有该组的缺陷地址被应用于用于检测存储器是否接收到有缺陷的列地址的比较器。 因此,在缺陷列所在的地方和将用于替换它的冗余列的位置之间建立相关性。 该相关性来自于AP的一组放大器的同时选择以及连接到这些放大器的一组缺陷列地址。
    • 7. 发明授权
    • Clock frequency doubler
    • 时钟频闪
    • US5111066A
    • 1992-05-05
    • US653633
    • 1991-02-12
    • Alain ArtieriSylvain Kritter
    • Alain ArtieriSylvain Kritter
    • H03K5/00H03K5/151
    • H03K5/1515H03K5/00006
    • A circuit for generating non-overlapping complementary clock signals at a double frequency from an input clock signal. An NAND flip-flop (2) has complementary outputs on which double frequency signals are available. A D-type flip-flop (3) receives on its clock input (H) one of the outputs of the NAND flip-flop, and has its output (Q.sub.D) coupled to its data input (D) through an inverter. Two Exclusive OR gates (XO1, XO2) receive on their first inputs the input clock signal and its complement, respectively, and on their second input the output of the D-type flip-flop. The outputs of the OR gates are connected to the inputs (E1 and E2) of the NAND flip-flop, respectively.
    • 一种用于从输入时钟信号以双倍频率产生非重叠互补时钟信号的电路。 NAND触发器(2)具有互补输出,双频信号可用于其上。 D型触发器(3)在其NAND触发器的输出之一的时钟输入(H)上接收,并且通过反相器将其输出(QD)与其数据输入(D)耦合。 两个异或门(XO1,XO2)分别在其第一个输入端接收输入时钟信号及其补码,并在其第二个输入端接收D型触发器的输出。 或门的输出分别连接到NAND触发器的输入(E1和E2)。