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1. 发明授权

US5148165A CMOS digital to analog signal converter circuit 失效
标题翻译： CMOS数模转换电路
公开(公告)号：US5148165A
公开(公告)日：1992-09-15
申请号：US451225
申请日：1989-12-15
申请人： Richard S. Phillips
发明人： Richard S. Phillips
IPC分类号： H03K17/687
CPC分类号： H03K17/6872
摘要： A digital to analog converter comprising a differential amplifier formed of a pair of similar conductivity type field effect transistors, one transistor being connected to a load for driving the load in synchronism with a digital input signal, means for applying a reference voltage to the gate of the second transistor, and a third field effect transistor of conductivity type complementary to said one transistor, connected with its source-drain circuit in series with the source-drain circuit of the second transistor to a second reference voltage, and means for driving the gates of said one and third transistors together with said digital input signal, whereby the first and third transistors are synchronously and oppositely driven to conduct and cut off, thus ensuring substantially no current flow in the second transistor while the first transistor is conducting.
摘要翻译：一种数模转换器，包括由一对类似导电型场效应晶体管构成的差分放大器，一个晶体管连接到用于与数字输入信号同步驱动负载的负载，用于将参考电压施加到栅极的装置第二晶体管和与所述一个晶体管互补的导电类型的第三场效应晶体管，其源极 - 漏极电路与第二晶体管的源极 - 漏极串联连接到第二参考电压，以及用于驱动栅极的装置所述第一和第三晶体管与所述数字输入信号一起，由此第一和第三晶体管被同步和相反地驱动以导通和切断，从而在第一晶体管导通的同时确保第二晶体管中基本上没有电流流动。

2. 发明授权

US4980862A Folded bitline dynamic ram with reduced shared supply voltages 失效
标题翻译：具有降低的共享电源电压的折叠位线动态RAM
公开(公告)号：US4980862A
公开(公告)日：1990-12-25
申请号：US268590
申请日：1988-11-08
申请人： Richard C. Foss
发明人： Richard C. Foss
IPC分类号： G11C11/4074 , G11C11/4094
CPC分类号： G11C11/4074 , G11C11/4094
摘要： A folded bitline dynamic RAM circuit with reduced shared supply voltages comprised of circuitry for applying full logic high and low supply voltages to respective bitlines during successive active cycles of the RAM circuit, and circuitry for applying reduced supply voltages to the bitlines during successive precharge cycles. By applying reduced supply voltages to the bitlines during the precharge cycles voltage stress on cell access transistors and sense amplifiers of the RAM circuit are reduced. The time required to share the charge residing on the bitline halves at the start of the active cycle is also reduced.
摘要翻译：具有降低的共享电源电压的折叠位线动态RAM电路，包括用于在RAM电路的连续有效周期期间将全逻辑高电平和低电源电压施加到相应位线的电路，以及用于在连续预充电周期期间将位电源施加减小的电源电压的电路。通过在预充电循环期间对位线施加减小的电源电压，RAM电路的单元存取晶体管和读出放大器的电压降低。在活动周期开始时分享驻留在位线一半的电荷所需的时间也减少了。

3. 发明授权

US5267201A High voltage boosted word line supply charge pump regulator for DRAM 失效
标题翻译：用于DRAM的高压升压字线供电电荷泵稳压器
公开(公告)号：US5267201A
公开(公告)日：1993-11-30
申请号：US680994
申请日：1991-04-05
申请人： Richard C. Foss , Peter B. Gillingham , Robert F. Harland , Valerie L. Lines
发明人： Richard C. Foss , Peter B. Gillingham , Robert F. Harland , Valerie L. Lines
IPC分类号： G11C11/407 , G05F3/20 , G11C5/14 , G11C8/08 , G11C11/4074 , G11C11/408 , H02M3/07 , G11C7/00
CPC分类号： G05F3/205 , G11C11/4074 , G11C11/4085 , G11C5/145 , G11C5/147 , G11C8/08 , H02M3/07
摘要： A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating drift tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.
摘要翻译：用于提供用于DRAM字线的输出电压的电路，其可用于驱动可高达2Vdd的存储器字线。升压电路中的晶体管完全切换，消除了如现有技术中Vtn的升压电压的降低。升压电容由Vdd充电，从而消除与时钟增压源和Vdd相关的漂移跟踪问题。调节器检测存储单元存取晶体管的复制品的传导电流，当达到操作存取晶体管的正确电压时，切断升压电路时钟振荡器。

4. 发明授权

US5198708A Transition detection circuit 失效
标题翻译：过渡检测电路
公开(公告)号：US5198708A
公开(公告)日：1993-03-30
申请号：US680745
申请日：1991-04-05
申请人： Peter B. Gillingham
发明人： Peter B. Gillingham
IPC分类号： G11C8/18 , H03K5/1534
CPC分类号： G11C8/18 , H03K5/1534
摘要： An address transition detection circuit which uses fast inverters in a delay line, avoiding filtering of input pulses and providing significant threshold voltage margin for the input address signal. A pair of gates connected to various points of the delay line detect at at least one point the presence of an address transition passing along the delay line.
摘要翻译：一种地址转换检测电路，其在延迟线中使用快速反相器，避免滤波输入脉冲并为输入地址信号提供显着的阈值电压裕度。连接到延迟线的各个点的一对门在至少一个点处检测到沿延迟线通过的地址转换的存在。

5. 发明授权

US5144223A Bandgap voltage generator 失效
标题翻译：带隙电压发生器
公开(公告)号：US5144223A
公开(公告)日：1992-09-01
申请号：US667880
申请日：1991-03-12
申请人： Peter B. Gillingham
发明人： Peter B. Gillingham
IPC分类号： G05F3/30
CPC分类号： G05F3/30 , Y10S323/907
摘要： A bandgap voltage generator useful in CMOS integrated circuits using intrinsic bipolar transistors. The generator is comprised of a pair of bipolar voltage generator which utilizes bipolar devices in a common collector configuration. Therefore for the first time a bandgap voltage reference using the intrinsic vertical bipolar transistor can be implemented in a CMOS chip without the need for an operational amplifier. In order to provide the above, an embodiment of the present invention is a bandgap voltage generator comprising a pair of bipolar transistors connected in common collector configuration with ratioed resistors on the emitters to define branch current and provide temperature compensation, and field effect transistors connected as source followers in series with the emitters of the bipolar transistors for establishing bandgap potential across the resisters and base-emitter junctions, a current comparator connected in series with the drains of the first pair of field effect transistors for controlling the emitter-collector currents in the bipolar transistors, the current comparator and the common collector being connected across a power source.
摘要翻译：一种带隙电压发生器，可用于使用本征双极型晶体管的CMOS集成电路。该发生器由一对双极性电压发生器组成，该发生器采用公共集电器配置的双极器件。因此，首次使用本征垂直双极晶体管的带隙电压参考可以在CMOS芯片中实现，而不需要运算放大器。为了提供上述，本发明的实施例是一种带隙电压发生器，其包括一对双极晶体管，其以公共集电极配置连接，在发射极上具有比例电阻器，以限定支路电流并提供温度补偿，并且将场效应晶体管连接为源极跟随器与双极晶体管的发射极串联，用于在电阻和基极 - 发射极结两端建立带隙电位，电流比较器与第一对场效应晶体管的漏极串联连接，用于控制发射极 - 集电极电流双极晶体管，电流比较器和公共集电极跨越电源连接。

6. 发明授权

US5093808A Folded bitline dynamic RAM with reduced shared supply voltages 失效
标题翻译：具有降低的共享电源电压的折叠双列动态RAM
公开(公告)号：US5093808A
公开(公告)日：1992-03-03
申请号：US585714
申请日：1990-09-19
申请人： Richard C. Foss
发明人： Richard C. Foss
IPC分类号： G11C11/4074 , G11C11/4094
CPC分类号： G11C11/4074 , G11C11/4094
摘要： A folded bitline dynamic RAM circuit with reduced shared supply voltages comprised of circuitry for applying full logic high and low supply voltages to respective bitlines during successive active cycles of the RAM circuit, and circuitry for applying reduced supply voltages to the bitlines during successive precharge cycles. By applying reduced supply voltages to the bitlines during the precharge cycles voltage stress on cell access transistors and sense amplifiers of the RAM circuit are reduced. The time required to share the charge residing on the bitline halves at the start of the active cycle is also reduced.

7. 发明授权

US5255232A DRAM cell plate and precharge voltage generator 失效
标题翻译： DRAM单元板和预充电电压发生器
公开(公告)号：US5255232A
公开(公告)日：1993-10-19
申请号：US680748
申请日：1991-04-05
申请人： Richard C. Foss , Valerie L. Lines
发明人： Richard C. Foss , Valerie L. Lines
IPC分类号： G11C11/4074 , G11C11/24
CPC分类号： G11C11/4074
摘要： A method and apparatus for precharging memory cell bit storage capacitors and bit lines of a DRAM from a single source. The storage capacitor reference plate is driven from a high impedance voltage divider, minimizing the effects of voltage supply noise, so that noise does not couple into the storage capacitor and turn on the associated capacitor access transistor. At the same time the bit line is driven from a low impedance drive, to enable it to maintain the bit line midpoint voltage. The bit line precharge voltage is referenced to the storage capacitor reference voltage providing good cell margin.
摘要翻译：一种用于从单个源预充电DRAM的存储单元位存储电容器和位线的方法和装置。存储电容器参考板由高阻抗分压器驱动，使电源噪声的影响最小化，使噪声不耦合到存储电容器中，并接通相关的电容器存取晶体管。同时，位线由低阻抗驱动驱动，使其能够保持位线中点电压。位线预充电电压参考存储电容参考电压，提供良好的单元余量。

8. 发明授权

US5027329A Addressing for large dynamic RAM 失效
标题翻译：寻址大型动态RAM
公开(公告)号：US5027329A
公开(公告)日：1991-06-25
申请号：US445448
申请日：1989-12-04
申请人： Richard C. Foss
发明人： Richard C. Foss
IPC分类号： G11C8/04 , G11C11/408
CPC分类号： G11C11/408 , G11C8/04
摘要： A DRAM semiconductor memory chip comprised of a matrix of rows and columns having a bit storage cell at each location, means for receiving row and column address bits in multiplexed form on a single address bus, the multiplexing arrangement being such that the number of column address bits exceeds the number of row address bits, whereby a system using the DRAM memory chip has access to an enlarged page size.
摘要翻译：一种由在每个位置具有位存储单元的行和列的矩阵构成的DRAM半导体存储器芯片，用于在单个地址总线上以多路复用形式接收行和列地址位的装置，所述复用布置使得列地址数位超过行地址位数，由此使用DRAM存储器芯片的系统可以访问扩大的页面大小。

9. 发明授权

US5305283A Dram column address latching technique 失效
标题翻译： Dram列地址锁定技术
公开(公告)号：US5305283A
公开(公告)日：1994-04-19
申请号：US680993
申请日：1991-04-05
申请人： Gregg M. Shimokura , Peter B. Gillingham
发明人： Gregg M. Shimokura , Peter B. Gillingham
IPC分类号： G11C8/18 , G11C11/408 , G11C8/00
CPC分类号： G11C8/18 , G11C11/4082 , G11C11/4087 , G11C8/06
摘要： Apparatus and a method for latching a column address in a DRAM, having increased speed and no race conditions. The method is comprised of the steps of receiving column select and column address input signals, enabling detection and indication, by generation of an indication signal, of the presence of each stable column address input signal upon the presence of a column select signal, summing the indication signals, and operating a latch by each of the column address input signals whereby a DRAM column can be addressed upon enabling by the summed indication signals, whereby the latching is not enabled without a first indication of the presence of a stable column address and whereby the first indication is prevented without the earlier presence of a column select signal.
摘要翻译：用于在DRAM中锁定列地址的装置和方法，具有增加的速度和没有竞争条件。该方法包括以下步骤：接收列选择和列地址输入信号，使得能够通过产生指示信号来检测和指示在存在列选择信号时每个稳定列地址输入信号的存在，指示信号，并且通过列地址输入信号中的每一个操作锁存器，由此可以在通过相加的指示信号启用时可以寻址DRAM列，由此在没有稳定列地址的存在的第一指示的情况下不启用锁存，并且由此在没有更早存在列选择信号的情况下，防止第一指示。

10. 发明授权

US5214602A Dynamic memory word line driver scheme 失效
标题翻译：动态内存字线驱动方案
公开(公告)号：US5214602A
公开(公告)日：1993-05-25
申请号：US680746
申请日：1991-04-05
申请人： Valerie L. Lines
发明人： Valerie L. Lines
IPC分类号： G11C11/407 , G11C8/08 , G11C11/408
CPC分类号： G11C11/4085 , G11C8/08
摘要： A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained A DRAM is comprised of bit lines and word lines, memory cells connected to the bit lines and word lines, each memory cell being comprised of an access field effect transistor (FET) having its source-drain circuit connected between a bit line and a high logic level voltage V.sub.dd bit charge storage capacitor, the field effect transistor having a gate connected to a corresponding word line; a high V.sub.pp supply voltage source which is in excess of high logic level voltage V.sub.dd plus one transistor threshold voltage but less than a transistor damaging voltage; means for selecting the word line and means having an input driven by the selecting means for applying the V.sub.pp supply voltage level directly to the word line through the source-drain circuit of an FET. Thus an above V.sub.dd voltage level on the word line is achieved without the use of double boot-strap circuits.
摘要翻译：准确地将字线（传输晶体管栅极）驱动电压控制到电压的电路，该电压被控制并且不显着大于驱动字线所需的电压。本发明的元件消除了对双引导带电路的需要，并且确保没有电压超过完全打开存储单元存取晶体管所需的电压。因此，避免了超过降低可靠性的电压，并且获得了精确的驱动电压。DRAM由位线和字线，连接到位线和字线的存储单元构成，每个存储单元包括存取场效应晶体管（FET），其源极 - 漏极电路连接在位线和高逻辑电平电压Vdd位电荷存储电容器之间，场效应晶体管具有连接到对应字线的栅极; 高Vpp电源电压超过高逻辑电平电压Vdd加一个晶体管阈值电压但小于晶体管损坏电压; 用于选择字线的装置和具有由选择装置驱动的输入的装置，用于通过FET的源极 - 漏极电路将Vpp电源电压直接施加到字线。因此，在不使用双引导电路的情况下实现字线上的Vdd电压电平。

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