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1. 发明授权

US3858187A Read only memory system 失效
标题翻译：只读存储系统
公开(公告)号：US3858187A
公开(公告)日：1974-12-31
申请号：US43262174
申请日：1974-01-11
申请人： GTE AUTOMATIC ELECTRIC LAB INC
发明人： LIGHTHALL J , TOY H
IPC分类号： G06F12/04 , G11C7/00 , G11C17/00
CPC分类号： G06F12/04
摘要： Read only memory system employing an array of memory elements each of which stores 256 8-bit word segments. Each program word to be read out of the system contains 20 bits. The first 8 bits of a program word are stored in a word segment of a first memory element and the second 8 bits are stored in the corresponding word segment of a second memory element. The last 4 bits are stored in 4 bit positions of the corresponding word segment of a third memory element. The other 4 bit positions of this word segment contain the last 4 bits of another program word which has its first 16 bits stored in two other memory elements. The desired program word is read out by addressing the appropriate word segment of every memory element of the array, and by applying memory element select signals to the three memory elements containing portions of the desired program word. The memory element select signal to the third memory element is generated by the memory element select signal to the first and second memory elements. Such a signal to the third memory element would also be generated if the other program word were the program word desired. The first 16 bits are read out of the two memory elements directly in parallel. The 4-bit portions of the two program words in the same word segment of the third memory element are read out to two separate gating arrangements. The memory element select signal which is applied to the first two memory elements is also applied to the gating arrangement receiving the 4-bit portion of the desired program word. Thus, the last 4 bits of the desired program word are read out through the one gating arrangement while the last 4 bits of the other program word from the same word segment of the third memory element are blocked by the other gating arrangement.
摘要翻译：只读存储器系统采用每个存储256个8位字段的存储器元件阵列。要读出的每个程序字都包含20位。程序字的前8位被存储在第一存储元件的字段中，第二8位存储在第二存储元件的相应字段中。最后4位存储在第三存储器元件的相应字段的4位位置。该字段的其他4位位置包含另一个程序字的最后4位，其前16位存储在另外两个存储器元件中。通过寻址阵列的每个存储元件的适当的字段以及通过将存储元件选择信号应用于包含所需程序字的部分的三个存储器元件来读出期望的程序字。通过到第一和第二存储器元件的存储元件选择信号产生到第三存储器元件的存储元件选择信号。如果其他程序字是所需的程序字，则也将产生到第三存储器元件的这种信号。前两个存储元件直接并行读出前16位。第三存储器元件的相同字段中的两个程序字的4位部分被读出到两个单独的选通装置。应用于前两个存储元件的存储元件选择信号也被应用于接收期望的程序字的4位部分的选通装置。因此，通过一个选通装置读出期望的程序字的最后4位，而来自第三存储元件的相同字段的另一个程序字的最后4位被另一个选通装置阻挡。

2. 发明授权

US3855580A Memory system including addressing arrangement 失效
标题翻译：包含寻址安排的记忆系统
公开(公告)号：US3855580A
公开(公告)日：1974-12-17
申请号：US43262274
申请日：1974-01-11
申请人： GTE AUTOMATIC ELECTRIC LAB INC
发明人： LIGHTHALL J , TOY H
IPC分类号： G06F12/06 , G11C7/00 , G11C17/00
CPC分类号： G06F12/0653
摘要： Read only memory system employing four arrays of memory elements, each memory element storing 256 8-bit word segments. Each memory element has address input connections for selectively addressing each word segment and a memory element select connection for enabling the memory element. Each memory element operates in response to a clock pulse at its clock input during a signal at its select connection to read out in parallel the 8 bits of the word segment addressed by signals at the address input connections. Address information bits are received in parallel and applied to a decoding arrangement. The decoding arrangement includes a group of gates which couple a first portion of the address bits to the address input connections of all the memory elements of the system. The decoding arrangement also includes a first decoder coupled to the select connections of all the memory elements of the system for enabling particular memory elements of each array as determined by the second portion of the address bits. A second decoder in the decoding arrangement produces a signal at one of four outputs as determined by a third portion of the address bits. These four outputs are connected to a source of clock pulses and gate a clock pulse to one of the four arrays depending on which output has the signal present. The clock pulse is applied to the clock inputs of all the memory elements of that array.
摘要翻译：只读存储器系统采用四个存储元件阵列，每个存储元件存储256个8位字段。每个存储器元件具有用于选择性地寻址每个字段的地址输入连接和用于启用存储器元件的存储元件选择连接。每个存储元件在其选择连接处的信号期间响应于其时钟输入处的时钟脉冲而工作以并行地读出由地址输入连接处的信号寻址的字段的8位。并行地接收地址信息比特并将其应用于解码装置。解码装置包括将地址位的第一部分耦合到系统的所有存储器元件的地址输入连接的一组门。解码装置还包括耦合到系统的所有存储器元件的选择连接的第一解码器，用于启用由地址位的第二部分确定的每个阵列的特定存储器元件。解码装置中的第二解码器在由地址位的第三部分确定的四个输出中的一个产生信号。这四个输出连接到时钟脉冲源，并根据哪个输出具有信号将时钟脉冲门控到四个阵列之一。时钟脉冲被施加到该阵列的所有存储器元件的时钟输入。

3. 发明授权

US3601702A High speed data transmission system utilizing nonbinary correlative techniques 失效
标题翻译：高速数据传输系统利用非线性相关技术
公开(公告)号：US3601702A
公开(公告)日：1971-08-24
申请号：US3601702D
申请日：1969-03-17
申请人： GTE AUTOMATIC ELECTRIC LAB INC
发明人： LENDER ADAM
IPC分类号： H04L25/48 , H04L25/497 , H03K13/256 , H03K13/34
CPC分类号： H04L25/497
摘要： A digital data transmission system which significantly increases the transmission rate of a binary data signal over a band limited transmission channel employs correlative techniques utilizing novel precoding for converting a binary input signal into a multilevel nonbinary correlative signal which is transmitted. Each level of the transmitted signal, seven being required to achieve a factor of eight improvement in transmission rate, represents a particular combination of the original binary digits, and introduction of correlative properties at the transmitter permits the original binary data to be recovered at the receiver with standard logic circuits without reference to the past history of the waveform. The correlative properties of the transmitted signal also permit error detection without adding redundant digits at the transmitter end. The bit speed capability of the concept is not limited to eight times that of a binary system but, in general, is equal to 21og2Q per Hertz in carrier applications, where Q is equal to the number of levels of a noncorrelative nonbinary signal and is an integer greater than two.

4. 发明授权

US3890468A Circuit arrangement for ground start coin operated telephones 失效
标题翻译：用于地面起动投币式电话的电路布置
公开(公告)号：US3890468A
公开(公告)日：1975-06-17
申请号：US42130173
申请日：1973-12-03
申请人： GTE AUTOMATIC ELECTRIC LAB INC
发明人： BURNS ROBERT V , HAMILTON RICHARD J
IPC分类号： H04M17/02
CPC分类号： H04M17/023
摘要： A circuit arrangement, utilizing a variable initial deposit rate totalizer for providing a ground start mode of operation or prepay coin telephones.
摘要翻译：一种电路装置，利用可变的初始存款率累加器来提供地面开始操作模式或预付硬币电话。

5. 发明授权

US3702469A Alarm circuit for indicating failure in redundant power supplies 失效
标题翻译：用于指示冗余电源故障的报警电路
公开(公告)号：US3702469A
公开(公告)日：1972-11-07
申请号：US3702469D
申请日：1971-09-03
申请人： GTE AUTOMATIC ELECTRIC LAB INC
发明人： GOLJA JOSEPH
IPC分类号： G01D3/08 , H01M10/48 , H02H3/20 , H02H3/24
CPC分类号： H02H3/243 , G01D3/08 , H01M10/48 , H02H3/20 , H02H3/24
摘要： The output voltages of a pair of dual polarity power supplies are coupled together through associated solid state alarm-sense circuits to common utilization equipment. Each alarm-sense circuit comprises a pair of switching transistors connected to associated voltage dividers that are connected across the output lines of a power supply; a pair of transistors connected in parallel; and a lamp. The output lines supporting the same polarity voltages are connected together through steering diodes that prevent one supply loading the other. The switching transistors detect increases and decreases in supply voltages that are greater than prescribed amounts. In each alarm-sense circuit, the parallel connected transistors are responsive to the operation of the switching transistors to light the lamp to indicate failure of the associated power supply. Output signals of the alarm-sense circuits are connected to a bell for also producing an audio alarm when a power supply fails. A zener diode is connected to a voltage divider for causing a switching transistor to detect a supply failure when the absolute values of the opposite polarity supply voltages from an associated power supply increase at the same rate.
摘要翻译：一对双极性电源的输出电压通过相关联的固态报警检测电路耦合到共同的利用设备。每个报警检测电路包括一对连接到相关联的分压器的开关晶体管，它们连接在电源的输出线上; 并联连接的一对晶体管; 和一盏灯。支持相同极性电压的输出线通过防止一个电源加载另一个的转向二极管连接在一起。开关晶体管检测大于规定量的电源电压的增加和减少。在每个报警检测电路中，并联的晶体管响应于开关晶体管的操作以点亮灯以指示相关电源的故障。报警检测电路的输出信号连接到一个钟，用于在电源出现故障时也产生音频报警。齐纳二极管连接到分压器，用于当相关电源的相反极性电源电压的绝对值以相同的速率增加时，使开关晶体管检测电源故障。

6. 发明授权

US3601787A Solder terminal and spring-wire solder form 失效
标题翻译：焊接终端和弹簧丝焊接形式
公开(公告)号：US3601787A
公开(公告)日：1971-08-24
申请号：US3601787D
申请日：1970-06-22
申请人： GTE AUTOMATIC ELECTRIC LAB INC
发明人： REIMER WILLIAM A
IPC分类号： H01R4/00 , H05K3/34 , H05K3/36 , H01R5/04
CPC分类号： H01R12/52 , H05K3/3447 , H05K3/368 , H05K2201/096 , H05K2201/10303 , H05K2201/10765 , H05K2201/10984 , H05K2203/0415
摘要： A solder form facilitates replacement of receptacle terminals that extend through blind connecting through-holes of a plurality of circuit boards. A hairpin conductor within the solder form spreads apart when the form is melted to carry solder to a replacement terminal and to the conductive surface of a throughhole.

7. 发明授权

US3601548A Switching matrix release delay circuit 失效
标题翻译：开关矩阵释放延迟电路
公开(公告)号：US3601548A
公开(公告)日：1971-08-24
申请号：US3601548D
申请日：1969-10-20
申请人： GTE AUTOMATIC ELECTRIC LAB INC
发明人： DRAAYER JOHANNES
IPC分类号： H04Q3/54 , H04Q3/42
CPC分类号： H04Q3/54
摘要： A multistage cross-point switching network is disclosed for use in a program controlled communication switching system. Each cross-point consists of a group of glass enclosed, sealed reeds around which are wound the operate and hold windings. The hold winding and a contact of the cross-point form a series path with the other cross-points of a network connection that is then held by appropriate potentials at each end. The network connection is released by interrupting this series path, along with the talking path conductors. To ensure that the talking conductors are interrupted first, the hold path includes a diode connected across the series path of cross-points to provide a current path to delay their release.

8. 发明授权

US3585318A Matrix card test circuit 失效
标题翻译：矩阵卡测试电路
公开(公告)号：US3585318A
公开(公告)日：1971-06-15
申请号：US3585318D
申请日：1969-07-25
申请人： GTE AUTOMATIC ELECTRIC LAB INC
发明人： FUCHS SIEGFRIED H
IPC分类号： H04Q1/24 , H04M3/22
CPC分类号： H04Q1/24
摘要： A circuit arrangement to be connected to a telephone system card mounted cross-point matrix for the purpose of determining if the cross-points in the matrix are in use, prior to removing the card for servicing. The included circuitry gives indications of the status of the cross-points being tested and prevents idle crosspoints or cross-points that go from a busy to idle condition from being seized for further usage in the telephone system.

9. 发明授权

US3894192A DX signaling circuit 失效
标题翻译： DX信号电路
公开(公告)号：US3894192A
公开(公告)日：1975-07-08
申请号：US49266674
申请日：1974-07-29
申请人： GTE AUTOMATIC ELECTRIC LAB INC
发明人： WISOTZKY OTTO G
IPC分类号： H04M7/00 , H04M7/10 , H04Q1/38
CPC分类号： H04M7/0096 , H04Q1/38
摘要： An electronic DX signaling circuit for detection of DC signals on a two-way telephone trunk circuit. A bridge network connects to a cable pair, and a voltage detection circuit connects to four junctions within the bridge circuit. The bridge receives the DC signaling from the cable, and the voltage detection circuit adds and subtracts four voltages within the bridge in such a way so as to recover the desired signaling information from the unwanted received signals.
摘要翻译：一种用于在双向电话中继电路上检测直流信号的电子DX信号电路。桥接网络连接到电缆对，电压检测电路连接到桥接电路内的四个接头。桥接器从电缆接收直流信号，电压检测电路以这种方式加载和减去桥内的四个电压，从而从不想要的接收信号中恢复所需信令信息。

10. 发明授权

US3601546A Selection of a time multiplex shared register and use of a common data buffer in a communication switching system 失效
标题翻译：选择时分多址共享寄存器和在通信交换系统中使用通用数据缓冲器
公开(公告)号：US3601546A
公开(公告)日：1971-08-24
申请号：US3601546D
申请日：1970-02-02
申请人： GTE AUTOMATIC ELECTRIC LAB INC
发明人： LEE DAVID K K
IPC分类号： H04Q3/54 , H04M3/22
CPC分类号： H04Q3/54
摘要： Each register-sender is assigned an individual junctor, an area of memory, and a recurring time slot of a multiplex cycle; and each during its time slot has use of common process control logic circuits which include a sequence state register. The registersender subsystem includes a data buffer for communication with a marker. Upon origination of a call the marker sends a call-forservice signal to a seizure gate of the data buffer. Another input of the seizure gate is the idle state output of the sequence state register, so that when the time slot of an idle register-sender occurs, the output of the gate sets a ''''key-tomarker'''' flip-flop and a ''''busy'''' flip-flop. This enables call data to be received from the marker and the sequence state to be advanced for that register-sender. The ''''key-to-marker'''' flipflop is reset at the end of the time slot, and again set during each occurrence thereof, while the ''''busy'''' flip-flop remains set, until the data reception is finished. A register-sender may also initiate seizure of the data buffer via the process control sequence state register during a call to send data to the marker. A ''''conditional busy'''' flip-flop permits queueing of one register-sender for use of the data buffer.

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