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1. 发明授权

US09829356B1 Method and apparatus for multi-channel sensor interface with programmable gain, offset and bias 有权
公开(公告)号：US09829356B1
公开(公告)日：2017-11-28
申请号：US15187730
申请日：2016-06-20
申请人： Exar Corporation
发明人： Steven Smith , Dale Wedel
IPC分类号： G01D18/00 , G01D5/16
CPC分类号： G01D18/008 , G01D5/16 , G05B19/0423
摘要： A highly integrated programmable sensor interface with improved sensor signal calibration and conditioning functions is described. The programmable sensor interface according to the present invention sensor interface provides programmable gain, digital offset correction and bias for one or more signal channels on one chip on a per channel basis. According to another aspect of the invention, the sensor interface provides reference voltage and sensor biasing by using an on-chip precision voltage regulator. According to one aspect of the invention, multiple inputs are multiplexed and each is applied to a variable gain instrumentation amplifier, which connects to the output. The offset of a given channel is controlled by an on-chip DAC which has multiple digital storage registers, allowing each channel to have a unique, stored offset. Offsets and gains are programmed externally.

2. 发明申请

US20120327952A1 ETHERNET TAG APPROACH TO SUPPORT NETWORKING TASK OFFLOAD 审中-公开
标题翻译：以太网标签方法支持网络任务卸载
公开(公告)号：US20120327952A1
公开(公告)日：2012-12-27
申请号：US13167586
申请日：2011-06-23
申请人： MANQING HUANG , ANDREW LACROIX
发明人： MANQING HUANG , ANDREW LACROIX
IPC分类号： H04L12/56
CPC分类号： H04L12/413
摘要： A two chip network adapter is used to implement offloaded networking tasks. The first chip is the main ethernet controller chip. The second chip implements the offloaded tasks. Communication between a host and the second chip is done by adding offload and completion tags to the ethernet frame header of frames associated with the offloaded networking task.
摘要翻译：双芯片网络适配器用于实现卸载的网络任务。第一个芯片是主要的以太网控制器芯片。第二个芯片实现卸载的任务。通过将卸载和完成标签添加到与卸载的网络任务相关联的帧的以太网帧头上来实现主机和第二芯片之间的通信。

3. 发明申请

US20120223691A1 DIGITAL PULSE-FREQUENCY MODULATION CONTROLLER FOR SWITCH-MODE POWER SUPPLIES WITH FREQUENCY TARGETING AND ULTRASONIC MODES 有权
标题翻译：用于具有频率指向和超声波模式的开关电源的数字脉冲频率调制控制器
公开(公告)号：US20120223691A1
公开(公告)日：2012-09-06
申请号：US13039154
申请日：2011-03-02
申请人： JASON WEINSTEIN , ZHENYU ZHAO , JINGQUAN CHEN
发明人： JASON WEINSTEIN , ZHENYU ZHAO , JINGQUAN CHEN
IPC分类号： G05F1/10
CPC分类号： H02M3/156 , H02M1/44 , H02M2001/0032 , Y02B70/16
摘要： A digital pulse controller uses digital logic to send pulses to a high side and low side switches of a switch-mode power supply converter. The digital logic uses a pulse frequency mode which includes a frequency targeting mode and an ultrasonic mode. The frequency targeting mode dynamically adjusts the size of the pulses in order to achieve a switching frequency within a desired band. The ultrasonic mode is switched into when the frequency of the pulses are at or below a threshold and the time of the pulses reaches a minimum threshold.
摘要翻译：数字脉冲控制器使用数字逻辑将脉冲发送到开关模式电源转换器的高侧和低侧开关。数字逻辑使用包括频率瞄准模式和超声波模式的脉冲频率模式。频率瞄准模式动态地调节脉冲的大小以便实现期望频带内的切换频率。当脉冲的频率处于或低于阈值并且脉冲的时间达到最小阈值时，超声模式被切换。

4. 发明授权

US08098090B2 Open-drain output buffer for single-voltage-supply CMOS 有权
标题翻译：用于单电源CMOS的漏极开路输出缓冲器
公开(公告)号：US08098090B2
公开(公告)日：2012-01-17
申请号：US12699239
申请日：2010-02-03
申请人： Hung Pham Le
发明人： Hung Pham Le
IPC分类号： G05F1/10
CPC分类号： H03K19/003 , H03K19/00315 , H03K19/0185
摘要： An open-drain output buffer is operative to sustain relatively high voltages applied to an output pad. The open-drain buffer includes a number of floating wells, output switching devices and corresponding well-bias selectors to ensure that no gate oxide sustains voltages greater than a predefined value. PMOS and NMOS well-bias selectors operate to select and provide an available highest or lowest voltage, respectively, to bias corresponding well-regions and ensure no device switching terminals are electrically over stressed. As output related terminals experience switching related voltage excursions, the well-bias selectors select alternate terminals to continue selection of the respective highest or lowest voltages available and provide correct well-biasing conditions. Voltage dividers are incorporated to generate well-biasing control voltages. By electrical coupling across maximal voltages, the voltage dividers generate reference voltages that induce proper selection of well-bias voltages to the floating wells.
摘要翻译：开漏输出缓冲器可操作以维持施加到输出焊盘的较高电压。漏极开路缓冲器包括多个浮置阱，输出开关器件和相应的阱偏置选择器，以确保没有栅氧化层保持大于预定值的电压。 PMOS和NMOS阱偏压选择器分别操作以选择和提供可用的最高或最低电压，以偏置相应的阱区，并且确保器件开关端子不被电过压。随着输出相关终端经历切换相关的电压偏移，阱偏置选择器选择备用端子以继续选择可用的相应最高或最低电压，并提供正确的良好偏置条件。并入分压器以产生良好偏置的控制电压。通过跨最大电压的电耦合，分压器产生引起对浮置阱的阱偏置电压的适当选择的参考电压。

5. 发明申请

US20110204862A1 DIGITAL CONTROL METHOD FOR IMPROVING HEAVY-TO-LIGHT (STEP DOWN) LOAD TRANSIENT RESPONSE OF SWITCH MODE POWER SUPPLIES 有权
标题翻译：用于改善开关模式电源的负载过渡响应的数字控制方法
公开(公告)号：US20110204862A1
公开(公告)日：2011-08-25
申请号：US12708871
申请日：2010-02-19
申请人： Aleksandar Prodic , Zhenyu Zhao
发明人： Aleksandar Prodic , Zhenyu Zhao
IPC分类号： G05F1/46
CPC分类号： H02M3/158
摘要： A method for improving heavy-to-light load transient response in low-power switch-mode power supplies is described. It uses a negative voltage input power rail and a digital controller with an extended duty ratio control value to provide faster discharging current slew rate in the switched mode power supplies (SMPS) inductor.
摘要翻译：描述了一种在低功率开关模式电源中改善重轻负载瞬态响应的方法。它使用负电压输入电源轨和具有扩展占空比控制值的数字控制器，以在开关模式电源（SMPS）电感器中提供更快的放电电流转换速率。

6. 发明授权

US07816958B2 Means to reduce the PLL phase bump caused by a missing clock pulse 有权
标题翻译：意味着减少由缺失的时钟脉冲引起的PLL相位凸起
公开(公告)号：US07816958B2
公开(公告)日：2010-10-19
申请号：US11744420
申请日：2007-05-04
申请人： James Toner Sundby
发明人： James Toner Sundby
IPC分类号： H03L7/06
CPC分类号： H03L7/0891
摘要： A PLL includes control circuitry adapted to detect missing pulses of a reference clock and to control an output voltage of a charge pump disposed in the PLL accordingly. A signal generated in response to the detection of a missing pulse is pulse-width limited and applied to the charge pump during a first period. The detection of the pulse-width limited signal is used to generate a first slew signal that is also pulse-width limited and applied to the charge pump during a second period. The detection of the first slew signal is used to generate a second slew signal that is also pulse-width limited and applied to the charge pump during a third period. The amount of current supplied by the charge pump during the second charging period is equal to a sum of currents withdrawn by the charge pump during the first and third time periods.
摘要翻译： PLL包括适于检测参考时钟的丢失脉冲并且相应地控制设置在PLL中的电荷泵的输出电压的控制电路。响应于检测到缺失脉冲产生的信号被脉冲宽度限制并在第一时段期间施加到电荷泵。脉冲宽度限制信号的检测用于产生也在脉冲宽度受限并在第二周期期间施加到电荷泵的第一回转信号。第一回转信号的检测用于产生也在脉冲宽度受限并在第三周期期间施加到电荷泵的第二回转信号。在第二充电期间由电荷泵提供的电流量等于在第一和第三时间段期间由电荷泵取出的电流的总和。

7. 发明申请

US20100117752A1 MULTI-CHANNEL DIGITAL PULSE WIDTH MODULATOR (DPWM) 有权
标题翻译：多通道数字脉宽调制器（DPWM）
公开(公告)号：US20100117752A1
公开(公告)日：2010-05-13
申请号：US12608186
申请日：2009-10-29
申请人： ERIC IOZSEF , IRV LUSTIGMAN , ABDELKARIM GADIRI
发明人： ERIC IOZSEF , IRV LUSTIGMAN , ABDELKARIM GADIRI
IPC分类号： H03K7/08
CPC分类号： H03L7/0812 , G06F1/025 , H03K7/08 , H03L7/0814
摘要： A multiple channel Digital Pulse Width Modulator (DPWM) can include a single delay locked loop with a delay line, the delay line producing a number of outputs. Circuitry can use a delay line mask to mask a portion of the delay line outputs to produce a modified outputs so as to prevent premature pulse width reset. Jitter tolerance look ahead circuits can prevent jitter from causing premature reset of pulse width modulated signals. The pulse width modulators can include multiple alternately used multiplexers so that the operation of the pulse width modulators is not affected by the load time of the multiplexers.
摘要翻译：多通道数字脉宽调制器（DPWM）可以包括具有延迟线的单个延迟锁定环，延迟线产生多个输出。电路可以使用延迟线掩模来屏蔽延迟线输出的一部分以产生修改的输出，以防止过早的脉冲宽度复位。抖动容限预测电路可以防止抖动引起脉宽调制信号的过早复位。脉冲宽度调制器可以包括多个交替使用的多路复用器，使得脉冲宽度调制器的操作不受复用器的加载时间的影响。

8. 发明授权

US07710174B2 Digital pulse-width modulator based on non-symmetric self-oscillating circuit 有权
标题翻译：基于非对称自振荡电路的数字脉宽调制器
公开(公告)号：US07710174B2
公开(公告)日：2010-05-04
申请号：US12034593
申请日：2008-02-20
申请人： Aleksandar Prodić , Kun Wang , Amir Parayandeh
发明人： Aleksandar Prodić , Kun Wang , Amir Parayandeh
IPC分类号： H03K7/08
CPC分类号： H03K7/08 , H02M3/156
摘要： A low-power digital pulse-width modulator (DPWM) architecture for high frequency dc-dc switch-mode power supplies (SMPS) is disclosed that is well-suited for integration in power management systems of small handheld devices. The DPWM can operate in a stand-alone mode, without external clock, and can be implemented on a portion of silicon area needed for other DPWM solutions. In addition it has low power consumption and provides a good linearity of the input-to-output characteristic, also not characteristic for other architectures.
摘要翻译：公开了一种用于高频直流 - 直流开关电源（SMPS）的低功耗数字脉宽调制器（DPWM）架构，非常适合集成在小型手持设备的电源管理系统中。 DPWM可以在独立模式下工作，无需外部时钟，可以在其他DPWM解决方案所需的一部分硅片上实现。此外，它具有低功耗，并且提供输入到输出特性的良好线性度，也不是其他架构的特征。

9. 发明授权

US07701976B2 Communications system with segmenting and framing of segments 失效
标题翻译：具有分段和分段的通信系统
公开(公告)号：US07701976B2
公开(公告)日：2010-04-20
申请号：US11021520
申请日：2004-12-22
申请人： Russell Homer , Khai Hoan Duong
发明人： Russell Homer , Khai Hoan Duong
IPC分类号： H04J3/24
CPC分类号： H04L47/36 , H04L12/427 , H04L47/10 , H04L47/13
摘要： A communications system comprising a segmenting mechanism configured to receive a plurality of payloads and divide each of the received payloads into segments, a framing mechanism configured to insert at least one of the segments from each of the plurality of payloads into a packet, a first interface configured to transmit the packet, and a second interface configured to transmit segment information about the segments in the packet.
摘要翻译：一种通信系统，包括分段机制，其被配置为接收多个有效负载并将所接收的有效载荷分成多个段;帧机制，被配置为将来自所述多个有效载荷中的每一个的所述段中的至少一个插入到分组中;第一接口被配置为发送分组，以及第二接口，被配置为发送关于分组中的分段的分段信息。

10. 发明授权

US07696912B2 Interrupt based multiplexed current limit circuit 有权
标题翻译：基于中断的多路复用电流限制电路
公开(公告)号：US07696912B2
公开(公告)日：2010-04-13
申请号：US12114693
申请日：2008-05-02
申请人： Dimitry Goder , Zongqi Hu , Kendra Nguyen
发明人： Dimitry Goder , Zongqi Hu , Kendra Nguyen
IPC分类号： H03M1/00
CPC分类号： H02M3/157 , H02M3/1584 , H02M2001/0009
摘要： A switching voltage regulator includes, in part, N output stages, a loop ADC, a multiplexer, a current ADC, and an interrupt block. The loop analog-to-digital converter receives the N output voltages each of which is associated with one of N channels. The loop ADC is adapted to vary a duty cycle of N signals each applied to one of the N output stages that generate the N output voltages. The interrupt block is adapted to enable the multiplexer to couple an output stage to the current ADC if a difference between voltages sensed at an output stage during at least two sampling times exceeds a predefined threshold value. The interrupt block may also be adapted to enable the multiplexer to couple an output stage to the current ADC block if a difference between a voltage sensed at the output stage and a reference voltage exceeds a predefined threshold value.
摘要翻译：开关电压调节器部分地包括N个输出级，环路ADC，多路复用器，电流ADC和中断块。环路模数转换器接收N个输出电压，每个N个输出电压与N个通道中的一个相关联。环路ADC适于改变每个施加到产生N个输出电压的N个输出级中的一个的N个信号的占空比。如果在至少两个采样时间期间在输出级感测的电压之间的差超过预定义的阈值，则中断块适于使多路复用器将输出级耦合到当前ADC。如果在输出级感测的电压与参考电压之间的差超过预定义的阈值，则中断块还可以适于使多路复用器将输出级耦合到当前ADC模块。

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