专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20200097442A1 EFFICIENT UTILIZATION OF SYSTOLIC ARRAYS IN COMPUTATIONAL PROCESSING 审中-公开
公开(公告)号：US20200097442A1
公开(公告)日：2020-03-26
申请号：US16241085
申请日：2019-01-07
申请人： Ceva D.S.P. Ltd.
发明人： Jeffrey Allan (Alon) Jacob (Yaakov) , Roni M. Sadeh
IPC分类号： G06F15/80 , G06F9/30
摘要： A system and method for performing computational processing by a systolic array. The systolic array including an array of processing elements (PEs) arranged in rows and columns; logic to perform a horizontal shift operation, wherein the horizontal shift operation is performed across the entire systolic array; and logic to mark columns of PEs as enabled or disabled, wherein the systolic array is horizontally divided into horizontal groups, and wherein when performing the horizontal shift operation, valid data that crosses from a first column of PEs of a first horizontal group to a second column of PEs of a second horizontal group is invalidated, wherein the first horizontal group is adjacent to the second horizontal group.

2. 发明授权

US10402196B2 Multi-dimensional sliding window operation for a vector processor, including dividing a filter into a plurality of patterns for selecting data elements from a plurality of input registers and performing calculations in parallel using groups of the data elements and coefficients 有权
公开(公告)号：US10402196B2
公开(公告)日：2019-09-03
申请号：US14708767
申请日：2015-05-11
申请人： Ceva D.S.P. Ltd.
发明人： Roni M. Sadeh , Noam Dvoretzki
IPC分类号： G06F9/30
摘要： A logic circuit in a processor including a plurality of input registers, each for storing a vector containing data elements, a coefficient register for storing a vector containing N coefficients, an output register for storing a result vector, and an arithmetic unit configured to: obtain a pattern for selecting N data elements from the plurality of input registers, select a plurality of groups of N data elements from the plurality of input registers in parallel, wherein each group is selected in accordance with the pattern, and wherein each group is shifted with respect to a previous selected group, perform an arithmetic operation between each of the selected groups and the coefficients in parallel, and store results of the arithmetic operations in the output register.

3. 发明申请

US20180210735A1 SYSTEM AND METHOD FOR USING A BRANCH MIS-PREDICTION BUFFER 审中-公开
公开(公告)号：US20180210735A1
公开(公告)日：2018-07-26
申请号：US15877408
申请日：2018-01-23
申请人： Ceva D.S.P. Ltd.
发明人： Jeffrey Allan (Alon) JACOB (YAAKOV) , Michael Boukaya
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3806 , G06F9/3808 , G06F9/381 , G06F9/3861
摘要： A system and method is provided for executing a conditional branch instruction. The system and method may include a branch predictor to predict one or more instructions that depend on the conditional branch instruction and a branch mis-prediction buffer to store correct instructions that were not predicted by the branch predictor during a branch mis-prediction.

4. 发明授权

US09952869B2 System and method for using a branch mis-prediction buffer 有权
公开(公告)号：US09952869B2
公开(公告)日：2018-04-24
申请号：US12611937
申请日：2009-11-04
申请人： Jeffrey Allan (Alon) Jacob (Yaakov) , Michael Boukaya
发明人： Jeffrey Allan (Alon) Jacob (Yaakov) , Michael Boukaya
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3806 , G06F9/381 , G06F9/3861
摘要： A system and method is provided for executing a conditional branch instruction. The system and method may include a branch predictor to predict one or more instructions that depend on the conditional branch instruction and a branch mis-prediction buffer to store correct instructions that were not predicted by the branch predictor during a branch mis-prediction.

5. 发明授权

US09391738B2 System and method for accelerating a maximum likelihood decoder in a MIMO system 有权
标题翻译：用于加速MIMO系统中的最大似然解码器的系统和方法
公开(公告)号：US09391738B2
公开(公告)日：2016-07-12
申请号：US14168397
申请日：2014-01-30
申请人： Ceva D.S.P. Ltd.
发明人： Noam Dvoretzki , Zeev Kaplan , Jeffrey Allan (Alon) Jacob (Yaakov)
IPC分类号： H04L27/06 , H04L1/00 , H04B7/04 , H04B7/08 , H04L25/03
CPC分类号： H04L1/0054 , H04B7/0413 , H04B7/0837 , H04L1/0047 , H04L25/03242 , H04L25/03891 , H04L2025/03426
摘要： A decoder to search a tree graph to decode a received signal. The tree graph may have a plurality of levels, each level having a plurality of nodes and each node representing a different value of an element of a candidate transmit signal corresponding to the received signal. The decoder may include a first module to execute a branch prediction at each branch node to select one of a plurality of candidate nodes stemming from the branch node that has a smallest distance increment, and a second module, running in parallel to the first module, to evaluate the branch prediction made by the first module at each branch node by computing an accumulated distance of the selected node. If the accumulated distance of the selected node is greater than or equal to a search radius, the first module may override the branch prediction and select an alternative candidate node.
摘要翻译：解码器，用于搜索树形图以解码所接收的信号。树图可以具有多个级别，每个级别具有多个节点，并且每个节点表示对应于接收到的信号的候选发射信号的元素的不同值。解码器可以包括第一模块，用于在每个分支节点处执行分支预测，以选择源自具有最小距离增量的分支节点的多个候选节点中的一个;以及与第一模块并行运行的第二模块，通过计算所选节点的累积距离来评估由每个分支节点处的第一模块进行的分支预测。如果所选节点的累积距离大于或等于搜索半径，则第一模块可以覆盖分支预测并选择替代候选节点。

6. 发明授权

US08320454B2 Fast sub-pixel motion estimation 有权
标题翻译：快速子像素运动估计
公开(公告)号：US08320454B2
公开(公告)日：2012-11-27
申请号：US12369849
申请日：2009-02-12
申请人： Adi Panzer
发明人： Adi Panzer
IPC分类号： H04N7/12
CPC分类号： H04N19/523
摘要： Embodiments of the invention are directed to a system and method for sub-pixel motion estimation for video encoding. The method includes providing a best match between a source frame and a reference frame by generating a plurality of non linear building surfaces, generating, in real time, an estimated matching criteria surface representing a matching criteria between the source frame and the reference frame based on the building surfaces and a plurality of sample points of an actual matching criteria surface and selecting, in real time, a position on the estimated matching criteria surface.
摘要翻译：本发明的实施例涉及用于视频编码的子像素运动估计的系统和方法。该方法包括通过生成多个非线性构建表面来提供源帧和参考帧之间的最佳匹配，实时地基于代表源帧和参考帧之间的匹配准则的估计匹配准则表面，基于建筑物表面和实际匹配准则表面的多个采样点，并实时选择估计的匹配准则表面上的位置。

7. 发明申请

US20060150171A1 Control words for instruction packets of processors and methods thereof 审中-公开
标题翻译：处理器指令包的控制字及其方法
公开(公告)号：US20060150171A1
公开(公告)日：2006-07-06
申请号：US11022852
申请日：2004-12-28
申请人： Yuval Sapir , Michael Boukaya , Roy Glasner , Eran Briman , Hagay Gellis
发明人： Yuval Sapir , Michael Boukaya , Roy Glasner , Eran Briman , Hagay Gellis
IPC分类号： G06F9/45
CPC分类号： G06F9/30181 , G06F9/30032 , G06F9/30145 , G06F9/30167 , G06F9/3828 , G06F9/3853 , G06F9/3891
摘要： An instruction packet having an extended machine language instruction may include at least a machine language instruction having encoded bits of an operation and a control word including bits of one or more extension fields. The structure and meaning of the extension fields may depend upon the extended machine language instruction. An association between an extension field and a machine language instruction may depend on the relative position of the extension field and the machine language instruction in the instruction packet.
摘要翻译：具有扩展机器语言指令的指令分组可以至少包括具有编码的操作位的机器语言指令和包括一个或多个扩展字段的位的控制字。扩展字段的结构和含义可能取决于扩展的机器语言指令。扩展字段和机器语言指令之间的关联可以取决于扩展字段和机器语言指令在指令包中的相对位置。

8. 发明申请

US20060149936A1 Processor core interface for external hardware modules and methods thereof 有权
标题翻译：用于外部硬件模块的处理器核心接口及其方法
公开(公告)号：US20060149936A1
公开(公告)日：2006-07-06
申请号：US11022850
申请日：2004-12-28
申请人： Michael Boukaya , Roy Glasner , Eran Briman
发明人： Michael Boukaya , Roy Glasner , Eran Briman
IPC分类号： G06F9/44
CPC分类号： G06F9/3885 , G06F9/30101 , G06F9/3867 , G06F9/3877 , G06F9/3891
摘要： A processor core architecture includes a cluster having at least a register file and predefined functional units having access to the register file. The architecture also includes an interface to one or more arbitrary functional units external to the processor core. The interface is to provide the arbitrary functional units with access to the register file.
摘要翻译：处理器核心架构包括具有至少寄存器文件的集群和具有对寄存器文件的访问的预定义功能单元。该架构还包括到处理器核心外部的一个或多个任意功能单元的接口。该接口是为任意功能单元提供对寄存器文件的访问。

9. 发明授权

US10306516B2 Rate matching for wireless communication 有权
公开(公告)号：US10306516B2
公开(公告)日：2019-05-28
申请号：US15438823
申请日：2017-02-22
申请人： Ceva D.S.P. Ltd.
发明人： David Levy
IPC分类号： H04W28/22 , H04L29/06 , H03M13/27 , H03M13/29 , H03M13/00 , H04L1/00
摘要： A method and a logic circuit for rate matching for three equally sized bit streams, including: prepending each of the bit streams with null bits; permuting the first two bit streams according to a first permutation pattern; permuting the third bit stream based on the first permutation pattern; transposing the three bit streams; shuffling the second and third bit streams; removing the null bits from the first bit stream and from the shuffled bit stream, wherein location of the null bits in the first bit stream is based only on a number of prepended null bits and the first permutation pattern and location of the null bits in the shuffled bit stream is based only on the number of prepended null bits, the first permutation pattern, and a null index related to the number of prepended null bits; and generating a combined bit stream from the three bit streams.

10. 发明授权

US10169040B2 System and method for sample rate conversion 有权
公开(公告)号：US10169040B2
公开(公告)日：2019-01-01
申请号：US15352598
申请日：2016-11-16
申请人： Ceva D.S.P. Ltd.
发明人： Hagay Rozin , Jeffery Allan (Alon) Jacob (Yaakov)
IPC分类号： G06F9/30 , G06F17/10
摘要： A system and method for performing sample rate conversion by an execution unit, including receiving an instruction, where the instruction comprises an irregular shifting pattern of data elements stored in a vector register, and shifting the data elements in the vector register according to the irregular shifting pattern. In case of upsampling the irregular shifting pattern includes an indication stating whether a memory element loads a data element from an immediate next memory element or from a second next memory element. In case of downsampling the irregular shifting pattern includes an indication stating whether a memory element in the input vector register loads a data element from an immediate next memory element, or whether the memory element loads a data element previously stored in a shadow vector register and the data element stored in the immediate next memory element is loaded into the shadow vector register.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式