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1. 发明授权

US10074742B2 MOS device with island region 有权
公开(公告)号：US10074742B2
公开(公告)日：2018-09-11
申请号：US14961582
申请日：2015-12-07
申请人： Alpha and Omega Semiconductor Limited
发明人： Anup Bhalla , Xiaobin Wang , Ji Pan , Sung-Po Wei
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/78 , H01L29/10 , H01L29/423 , H01L29/66 , H01L29/872 , H01L21/265 , H01L29/06 , H01L29/165 , H01L29/417 , H01L29/45 , H01L29/47
CPC分类号： H01L29/7806 , H01L21/26513 , H01L21/26586 , H01L29/0623 , H01L29/1083 , H01L29/1095 , H01L29/165 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66143 , H01L29/66727 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7813 , H01L29/8725
摘要： A semiconductor device formed on a semiconductor substrate, comprising: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; an active region; and an island region under the contact trench and disconnected from the body, the island region having an opposite polarity as the epitaxial layer. The active region comprises: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and the body; and an active region contact electrode disposed within the active region contact trench.

2. 发明授权

US09236450B2 Fabrication of MOS device with schottky barrier controlling layer 有权
标题翻译：用肖特基势垒控制层制造MOS器件
公开(公告)号：US09236450B2
公开(公告)日：2016-01-12
申请号：US14300529
申请日：2014-06-10
申请人： Alpha & Omega Semiconductor Limited
发明人： Anup Bhalla , Xiaobin Wang , Ji Pan , Sung-Po Wei
IPC分类号： H01L21/8234 , H01L29/66 , H01L29/10 , H01L29/78 , H01L29/872 , H01L21/265 , H01L29/06 , H01L29/165 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/47
CPC分类号： H01L29/7811 , H01L21/26513 , H01L21/26586 , H01L29/0623 , H01L29/1083 , H01L29/1095 , H01L29/165 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66143 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7809 , H01L29/7813 , H01L29/8725
摘要： Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body; forming a source; forming an active region contact trench that extends through the source and the body into a drain; forming a Schottky barrier controlling layer in the epitaxial layer in bottom region of the active region contact trench; and disposing a contact electrode within the active region contact trench. The Schottky barrier controlling layer controls Schottky barrier height of a Schottky diode formed by the contact electrode and the drain.
摘要翻译：制造半导体器件包括：在覆盖半导体衬底的外延层中形成栅极沟槽; 在栅极沟槽中沉积栅极材料; 形成身体形成一个来源; 形成有源区接触沟槽，其延伸穿过所述源和所述本体进入漏极; 在有源区接触沟槽的底部区域的外延层中形成肖特基势垒控制层; 以及将接触电极设置在有源区接触沟槽内。肖特基势垒控制层控制由接触电极和漏极形成的肖特基二极管的肖特基势垒高度。

3. 发明授权

US07667264B2 Shallow source MOSFET 有权
标题翻译：浅源MOSFET
公开(公告)号：US07667264B2
公开(公告)日：2010-02-23
申请号：US10952231
申请日：2004-09-27
申请人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
发明人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device comprises a drain, a body in contact with the drain, the body having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a trench extending through the source and the body to the drain, and a gate disposed in the trench, having a gate top surface that extends substantially above the body top surface. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.
摘要翻译：半导体器件包括漏极，与漏极接触的主体，主体具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中，延伸穿过源和主体的沟槽并且设置在沟槽中的门具有大致在主体顶表面上方延伸的门顶表面。一种制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成通过硬掩模的沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量延伸超过顶部衬底表面，并且去除硬掩模以留下基本上在顶部衬底表面上方延伸的栅极结构。

4. 发明授权

US07622796B2 Semiconductor package having a bridged plate interconnection 有权
标题翻译：具有桥接板互连的半导体封装
公开(公告)号：US07622796B2
公开(公告)日：2009-11-24
申请号：US11906136
申请日：2007-09-28
申请人： Lei Shi , Ming Sun , Kai Liu
发明人： Lei Shi , Ming Sun , Kai Liu
IPC分类号： H01L23/02
CPC分类号： H01L23/49524 , H01L23/49562 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/37011 , H01L2224/371 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73219 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, and a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source contacts. A bridged source plate interconnection has a bridge portion, valley portions disposed on either side of the bridge portion, plane portions disposed on either side of the valley portions and the bridge portion, and a connection portion depending from one of the plane portions, the bridged source plate interconnection connecting the source lead with the plurality of metalized source contacts. The bridge portion is disposed in a plane above the plane of the valley portions while the plane portions are disposed in a plane intermediate the plane of the bridge portion and the plane of the valley portions.
摘要翻译：公开了半导体封装。封装包括具有漏极，源极和栅极引线的引线框架以及耦合到引线框架的半导体管芯，该半导体管芯具有多个金属化源极触点。桥接源极板互连具有桥接部分，设置在桥接部分的任一侧上的谷部分，设置在谷部分和桥接部分两侧的平面部分以及从平面部分之一悬挂的连接部分，将源极引线与多个金属化源触点连接的源极板互连。桥面部分设置在平坦部分的平面上方的平面中，而平面部分设置在桥接部分的平面和谷部的平面之间的平面中。

5. 发明公开

US20240363743A1 IGBT DEVICE AND PREPARATION METHOD THEREOF 审中-公开
公开(公告)号：US20240363743A1
公开(公告)日：2024-10-31
申请号：US18769355
申请日：2024-07-10
申请人： CHONGQING ALPHA AND OMEGA SEMICONDUCTOR LIMITED
发明人： XIAOFENG QIN , LIANG SHI , WEI HU
IPC分类号： H01L29/739 , H01L23/544 , H01L29/66
CPC分类号： H01L29/7395 , H01L23/544 , H01L29/66333 , H01L2223/5446
摘要： An IGBT device and a preparation method thereof are provided. The preparation method comprises steps A-E. The step A comprises preparing epitaxial layers. The step B comprises preparing a front terminal structure. The high-density trenches comprise cell active trenches, cell pseudo trenches, and scribe line trenches. The step C comprises preparing a front MOSFET structure having high-density trenches. The step D comprises preparing a circuit link layer and a passivation layer. The step E comprises preparing back structures of the IGBT device. The preparation method solves a warpage problem when producing IGBT devices on a large-size wafer. At the same time, a depth of a buffer layer of the IGBT device and a concentration of a first element in the buffer layer are easy to adjust, which fully meets requirements for trench density, trench type, and buffer layer, and improves a yield rate of the IGBT devices.

6. 发明公开

US20230282636A1 DEVICE INTEGRATING TRENCH TYPE POWER DEVICE AND SOURCE CAPACITOR AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20230282636A1
公开(公告)日：2023-09-07
申请号：US18316245
申请日：2023-05-12
申请人： CHONGQING ALPHA AND OMEGA SEMICONDUCTOR LIMITED
发明人： YI ZHAO , LIANG SHI
IPC分类号： H01L27/02 , H01L21/8234
CPC分类号： H01L27/0255 , H01L21/823418 , H01L21/823475
摘要： A device integrating a trench type power device and a source capacitor and a manufacturing method of the device integrating the trench type power device and the source capacitor are provided, which relate to a technical field of manufacturing power semicondutor devices. The manufacturing method includes steps of preparing a cellular structure, preparing contact holes and tungsten bolts, accessing an electro-static discharge (ESD) diode and an integrated capacitor into the trench type power device, and depositing a passivation layer, etching a pad region, and performing wire bonding, which integrates the trench type power device and the source capacitor. Since no other masks are additionally added, a cost of the trench type power device and the manufacturing method thereof is controllable, and the device integrating the trench type power device and the source capacitor reduces use of external capacitors, thereby reducing an occupied area of a printed circuit board.

7. 发明授权

US08928079B2 MOS device with low injection diode 有权
标题翻译：具有低注入二极管的MOS器件
公开(公告)号：US08928079B2
公开(公告)日：2015-01-06
申请号：US13610758
申请日：2012-09-11
申请人： Anup Bhalla , Xiaobin Wang , Ji Pan , Sung-Po Wei
发明人： Anup Bhalla , Xiaobin Wang , Ji Pan , Sung-Po Wei
IPC分类号： H01L29/66 , H01L29/10 , H01L29/78 , H01L21/265 , H01L29/06 , H01L29/165 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/47
CPC分类号： H01L29/1095 , H01L21/26586 , H01L29/0623 , H01L29/165 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813
摘要： A semiconductor device is formed on a semiconductor substrate. The device includes: a drain; an epitaxial layer overlaying the drain, wherein a drain region extends into the epitaxial layer; and an active region. The active region includes: a body disposed in the epitaxial layer, having a body top surface; a source embedded in the body, extending from the body top surface into the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and into the body; and an active region contact electrode disposed within the active region contact trench. A layer of body region separates the active region contact electrode from the epitaxial layer, and a low injection diode is formed below a body/drain junction.
摘要翻译：半导体器件形成在半导体衬底上。该装置包括：排水管; 覆盖所述漏极的外延层，其中漏区延伸到所述外延层中; 和活跃区域。有源区包括：设置在外延层中的具有主体顶表面的主体; 嵌入在体内的源体，从身体顶面延伸到体内; 延伸到外延层中的栅极沟槽; 设置在栅极沟槽中的栅极; 有源区接触沟槽延伸穿过该源并进入体内; 以及设置在有源区接触沟槽内的有源区接触电极。主体区域将有源区接触电极与外延层分开，并且在主体/漏极结下方形成低注入二极管。

8. 发明授权

US08008151B2 Shallow source MOSFET 有权
标题翻译：浅源MOSFET
公开(公告)号：US08008151B2
公开(公告)日：2011-08-30
申请号：US11983769
申请日：2007-11-09
申请人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
发明人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.
摘要翻译：一种制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成通过硬掩模的沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量延伸超过顶部衬底表面，并且去除硬掩模以留下基本上在顶部衬底表面上方延伸的栅极结构。

9. 发明公开

US20240222420A1 TRENCH POWER DEVICE INTEGRATED WITH INDUCTOR AND MANUFACTURING METHOD THEREFOR 审中-公开
公开(公告)号：US20240222420A1
公开(公告)日：2024-07-04
申请号：US18427757
申请日：2024-01-30
申请人： CHONGQING ALPHA AND OMEGA SEMICONDUCTOR LIMITED
发明人： BING MEI , YI ZHAO , LIANG SHI
IPC分类号： H01F17/00
CPC分类号： H01L28/10
摘要： The present disclosure relates to a technical filed of power devices and manufacturing of semiconductors, and in particular to a manufacturing method for trench power device integrated with inductor and a trench power device integrated with inductor manufactured thereby, and the manufacturing method includes: forming a cell structure and an integrated inductor, defining contact holes; C, forming a circuit link layer, and forming a passivation layer.

10. 发明公开

US20240178275A1 SUPER-JUNCTION POWER DEVICE HAVING ADJUSTABLE RESISTORS CONNECTED IN PARALLEL BETWEEN GATES AND SOURCES AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20240178275A1
公开(公告)日：2024-05-30
申请号：US18432078
申请日：2024-02-05
申请人： CHONGQING ALPHA AND OMEGA SEMICONDUCTOR LIMITED
发明人： WEI HU
IPC分类号： H01L29/06 , H01L21/02 , H01L21/311 , H01L21/3115 , H01L21/3213
CPC分类号： H01L29/0688 , H01L21/0262 , H01L21/31144 , H01L21/31155 , H01L21/3213 , H01L28/20
摘要： A method of manufacturing a super-junction power device having adjustable resistors connected in parallel between a gate and a source; and the super-junction power device obtained by performing the method are provided. The method includes: preparing a unit cell and the adjustable resistors connected in parallel between the gate and the source of the super-junction power device; preparing contact holes; preparing metal wires; and preparing a passivation layer.

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