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1. 发明授权

US08738856B2 System for handling memory requests and method thereof 有权
标题翻译：用于处理存储器请求的系统及其方法
公开(公告)号：US08738856B2
公开(公告)日：2014-05-27
申请号：US11739322
申请日：2007-04-24
申请人： Michael Frank , Santiago Fernandez-Gomez , Robert W. Laker , Aki Niimura
发明人： Michael Frank , Santiago Fernandez-Gomez , Robert W. Laker , Aki Niimura
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/1642
摘要： A system and methods are shown for handling multiple target memory requests. Memory read requests generated by a peripheral component interconnect (PCI) client are received by a PCI bus controller. The PCI bus controller passes the memory request to a memory controller used to access main memory. The memory controller passes the memory request to a bus interface unit used to access cache memory and a processor. The bus interface unit determines if cache memory can be used to provide the data associated with the PCI client's memory request. While the bus interface unit determines if cache memory may be used, the memory controller continues to process the memory request to main memory. If cache memory can be used, the bus interface unit provides the data to the PCI client and sends a notification to the memory controller. The memory controller identifies the memory request, or returned data associated with the request, and discards it to ensure no data is returned to the bus controller from the memory controller. Once the data is received from the bus interface unit, the bus controller is free to send new memory read requests to the memory controller.
摘要翻译：显示了用于处理多个目标存储器请求的系统和方法。由PCI总线控制器接收由外围组件互连（PCI）客户机产生的存储器读取请求。 PCI总线控制器将存储器请求传递给用于访问主存储器的存储器控制器。存储器控制器将存储器请求传递到用于访问高速缓存存储器和处理器的总线接口单元。总线接口单元确定是否可以使用高速缓存存储器来提供与PCI客户机的存储器请求相关联的数据。当总线接口单元确定是否可以使用高速缓冲存储器时，存储器控制器继续处理对主存储器的存储器请求。如果可以使用高速缓冲存储器，则总线接口单元向PCI客户端提供数据，并向存储器控制器发送通知。存储器控制器识别与请求相关联的存储器请求或返回的数据，并丢弃它，以确保没有数据从存储器控制器返回总线控制器。一旦从总线接口单元接收到数据，总线控制器就可以向存储器控制器发送新的存储器读请求。

2. 发明授权

US08681160B2 Synchronizing multiple cards in multiple video processing unit (VPU) systems 有权
标题翻译：在多个视频处理单元（VPU）系统中同步多个卡
公开(公告)号：US08681160B2
公开(公告)日：2014-03-25
申请号：US11139744
申请日：2005-05-27
申请人： Syed Athar Hussain , James Hunkins , Jacques Vallieres
发明人： Syed Athar Hussain , James Hunkins , Jacques Vallieres
IPC分类号： G06F15/16
CPC分类号： G06T1/20
摘要： Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module controls a phase alignment between the processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels.
摘要翻译：提供系统和方法来处理数据。系统和方法包括每个耦合以接收命令和数据的多个处理器，其中命令和/或数据对应于包括多个像素的视频帧。另外，互连模块被耦合以接收对应于来自多个处理器中的每一个的帧的处理的数据。互连模块控制处理器之间的相位对准。互连模块基于预定的像素特性从一个处理器的处理数据中选择帧的像素，并输出包括所选择的像素的帧。

3. 发明授权

US08677416B2 Method, system and software for display of multiple media channels 有权
标题翻译：用于显示多个媒体频道的方法，系统和软件
公开(公告)号：US08677416B2
公开(公告)日：2014-03-18
申请号：US09908039
申请日：2001-07-17
申请人： Jitesh Arora
发明人： Jitesh Arora
IPC分类号： G06F3/00 , G06F13/00 , H04N5/445
CPC分类号： H04H60/65 , H04H60/73 , H04N5/44543 , H04N21/44222 , H04N21/4532 , H04N21/454 , H04N21/4622 , H04N21/4661 , H04N21/4667 , H04N21/4755 , H04N21/482 , H04N21/8146 , H04N21/84
摘要： A method, system, and software for improved display of multiple media channels are disclosed herein. A system may be used to select, independent of direct user input, a subset of a plurality of media channels based on a user's viewing pattern. The system can include one or more media sources, a media processing system, and a display device, as well as a method for its use. The media processing system receives a plurality of media channels from the one or more media sources. One or more attributes associated with each media channel are compared with a user's viewing pattern determined independent of direct user input by the media processing system. A surf list is generated from the plurality of media channels, where the surf list includes a subset of the plurality of media channels having one or more attributes that are congruent with the user's viewing pattern. A portion, such as a still image, of each media channel in the surf list is output to an output device, such as a display device or storage device. The portions can be displayed simultaneously in a grid on the screen of the display device; the portions can be displayed individually in sequence; or displayed using a combination thereof.
摘要翻译：本文公开了用于改进多媒体信道显示的方法，系统和软件。基于用户的观看模式，可以使用系统来独立于直接用户输入来选择多个媒体信道的子集。该系统可以包括一个或多个媒体源，媒体处理系统和显示设备，以及其使用方法。媒体处理系统从一个或多个媒体源接收多个媒体信道。将与每个媒体信道相关联的一个或多个属性与用媒体处理系统直接用户输入独立确定的用户观看模式进行比较。从多个媒体频道生成冲浪列表，其中冲浪列表包括具有与用户的观看模式一致的一个或多个属性的多个媒体频道的子集。冲浪列表中的每个媒体频道的诸如静止图像的一部分被输出到诸如显示设备或存储设备的输出设备。这些部分可以在显示装置的屏幕上的网格中同时显示; 这些部分可以依次单独显示; 或使用其组合显示。

4. 发明授权

US08666712B2 Physical simulations on a graphics processor 有权
标题翻译：图形处理器上的物理模拟
公开(公告)号：US08666712B2
公开(公告)日：2014-03-04
申请号：US11491169
申请日：2006-07-24
申请人： Avi I. Bleiweiss , Gerard S. Baron
发明人： Avi I. Bleiweiss , Gerard S. Baron
IPC分类号： G06G7/48
CPC分类号： G06F17/5009 , A63F13/00 , A63F2300/203 , A63F2300/64 , A63F2300/643
摘要： The present invention is directed to a method, computer program product, and system for performing physics simulations on at least one graphics processor unit (GPU). The method includes the following steps. First, data representing physical attributes associated with at least one mesh are mapped into a plurality of memory arrays to set up of a linear system of equations that governs motion of the at least one mesh depicted in a scene. Then, computations are performed on the data in the plurality of memory arrays using at least one pixel processor to solve the linear system of equations for an instant of time, wherein modified data representing the solution to the linear system of equations for the instant of time are stored in the plurality of memory arrays.
摘要翻译：本发明涉及用于在至少一个图形处理器单元（GPU）上执行物理模拟的方法，计算机程序产品和系统。该方法包括以下步骤。首先，表示与至少一个网格相关联的物理属性的数据被映射到多个存储器阵列中，以建立一个管理场景中描绘的至少一个网格的运动的线性方程组。然后，使用至少一个像素处理器对多个存储器阵列中的数据执行计算，以解决瞬时时间的线性方程组，其中修改的数据表示时间线性方程组的解存储在多个存储器阵列中。

5. 发明授权

US08281183B2 Apparatus with redundant circuitry and method therefor 有权
标题翻译：具有冗余电路的装置及其方法
公开(公告)号：US08281183B2
公开(公告)日：2012-10-02
申请号：US12509803
申请日：2009-07-27
申请人： Michael Mantor , Ralph Clayton Taylor , Robert Scott Hartog
发明人： Michael Mantor , Ralph Clayton Taylor , Robert Scott Hartog
IPC分类号： G06F11/00
CPC分类号： G06F11/2028 , G06F11/2038 , G06F11/2048
摘要： An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.
摘要翻译：具有电路冗余的装置包括一组并行算术逻辑单元（ALU），冗余并行ALU，输入数据移位逻辑，其耦合到该组并行ALU并且可操作地耦合到冗余并行ALU。输入数据移位逻辑将有缺陷的ALU的输入数据沿第一方向移动到该组中的相邻ALU。当相邻的ALU是组中的最后一个或结束ALU时，移位逻辑继续将没有故障的结束ALU的输入数据移动到冗余并行ALU。冗余的并行ALU然后对有缺陷的ALU进行操作。输出数据移位逻辑耦合到并行冗余ALU和所有其他ALU输出的输出，以使输出数据在与输入移位逻辑相反的方向上相反的方向上移位，以重新输出用于继续处理的数据输出，包括用于存储或用于由其他电路进一步处理。

6. 发明授权

US07970956B2 Graphics-processing system and method of broadcasting write requests to multiple graphics devices 有权
标题翻译：向多个图形设备广播写入请求的图形处理系统和方法
公开(公告)号：US07970956B2
公开(公告)日：2011-06-28
申请号：US11389945
申请日：2006-03-27
申请人： Anthony Asaro , Bo Liu
发明人： Anthony Asaro , Bo Liu
IPC分类号： G06F3/00 , G06F15/16 , G06F12/00
CPC分类号： G06F13/404
摘要： Described are a system and method for broadcasting write requests to a plurality of graphics devices. A different address range of graphics device addresses is associated with each graphics device of the plurality of graphics devices. A controller receives a write request directed to a memory address and generates a plurality of graphics device addresses based on the memory address of the write request when the memory address is within a particular range of broadcast addresses. An offset may be applied to a reference address in each address range associated with one of the graphics devices when generating the plurality of graphics device addresses. The write request is forwarded to each graphics device of the plurality of graphics devices associated with one of the generated graphics device addresses.
摘要翻译：描述了一种用于向多个图形设备广播写入请求的系统和方法。图形设备地址的不同地址范围与多个图形设备中的每个图形设备相关联。当存储器地址在广播地址的特定范围内时，控制器接收针对存储器地址的写请求并且基于写请求的存储器地址生成多个图形设备地址。当生成多个图形设备地址时，偏移量可以应用于与一个图形设备相关联的每个地址范围中的参考地址。将写请求转发到与所生成的图形设备地址之一相关联的多个图形设备中的每个图形设备。

7. 发明授权

US07969512B2 Memory bandwidth amortization 有权
标题翻译：内存带宽摊销
公开(公告)号：US07969512B2
公开(公告)日：2011-06-28
申请号：US11467755
申请日：2006-08-28
申请人： Paul Wiercienski , Chris Wiesner , Oswin Hall
发明人： Paul Wiercienski , Chris Wiesner , Oswin Hall
IPC分类号： H04N9/64
CPC分类号： H04N19/59 , H04N19/427 , H04N19/428 , H04N19/44
摘要： A system for processing video information, the system including a memory configured to store video information, a memory controller coupled to the memory and configured to receive memory requests for the video information, a first video signal processing client coupled to the memory controller. The first video signal processing client including a video signal processor, a buffer coupled to the video signal processor, and a memory request module coupled to the memory controller and to the buffer, the memory request module being configured to submit amortized memory requests to the memory controller.
摘要翻译：一种用于处理视频信息的系统，所述系统包括被配置为存储视频信息的存储器，耦合到所述存储器并被配置为接收对所述视频信息的存储器请求的存储器控制器，耦合到所述存储器控制器的第一视频信号处理客户端。第一视频信号处理客户机包括视频信号处理器，耦合到视频信号处理器的缓冲器以及耦合到存储器控制器和缓冲器的存储器请求模块，该存储器请求模块被配置为向存储器提交摊销的存储器请求控制器。

8. 发明授权

US07698493B2 Methods and apparatus for translating write request messages in a computing system 有权
标题翻译：在计算系统中翻译写请求消息的方法和装置
公开(公告)号：US07698493B2
公开(公告)日：2010-04-13
申请号：US11162169
申请日：2005-08-31
申请人： Anthony Asaro
发明人： Anthony Asaro
IPC分类号： G06F13/42 , G06F13/20 , G06F13/36
CPC分类号： G06F13/4027
摘要： Methods and apparatus are disclosed to translate memory write requests to be transmitted from a first processor to a second processor in a computing system, such as between a CPU and a Southbridge, as an example. A method includes generating a memory write request in a second protocol responsive to a memory write request of a first protocol, the first protocol supporting a first memory write command type and a second memory write command type, the second protocol supporting only the first memory write command type. The method also includes inserting a predefined code in the memory write request in the generated memory write request in the second protocol to produce a translated memory write request. The method may also include receiving the memory write request from the first processor where the memory write request is operable according to the first protocol having at least first and second memory write command types. The predefined code in the received memory write request is then used to determine the type of memory write request (posted or non-posted).
摘要翻译：作为示例，披露了将计算系统（例如CPU和南桥之间）中的第一处理器传送到第二处理器的存储器写入请求的方法和装置。一种方法包括响应于第一协议的存储器写入请求而在第二协议中生成存储器写入请求，第一协议支持第一存储器写入命令类型和第二存储器写入命令类型，第二协议仅支持第一存储器写入命令类型。该方法还包括在第二协议中生成的存储器写入请求中的存储器写入请求中插入预定义的代码以产生转换的存储器写入请求。该方法还可以包括从第一处理器接收存储器写请求，其中存储器写入请求可根据具有至少第一和第二存储器写命令类型的第一协议来操作。接收到的存储器写入请求中的预定义代码然后用于确定存储器写请求的类型（发布或未发布）。

9. 发明授权

US07636095B2 Pixel delta interpolation method and apparatus 有权
标题翻译：像素三角插值方法和装置
公开(公告)号：US07636095B2
公开(公告)日：2009-12-22
申请号：US10236089
申请日：2002-09-06
申请人： Laurent Lefebvre , Stephen L. Morein , Jay C. Wilkinson
发明人： Laurent Lefebvre , Stephen L. Morein , Jay C. Wilkinson
IPC分类号： G09G5/00
CPC分类号： G06T11/203
摘要： A method for rendering an object including receiving a pixel tile representing a portion of a primitive to be rendered, determining attributes of a reference pixel within the pixel tile, and determining the attributes of neighboring pixels within the pixel tile based on barycentric differences relative to the reference pixel is disclosed. A circuit for calculating at least one attribute of an object to be rendered includes an initial calculation circuit providing full precision reference pixel attribute data in response to a pixel tile that defines at least a portion of the object; and a derivative circuit, operatively coupled to the initial calculation circuit, providing reduced precision neighboring pixel attribute data in response to the pixel tile. The derivative circuit includes a plurality of pixel attribute sub-circuits or components, which determine the attribute values of neighboring pixels within the pixel tile at a precision less than that of the precision used to define the reference pixel.
摘要翻译：一种用于渲染对象的方法，包括接收表示要渲染的原语的一部分的像素块，确定所述像素块内的参考像素的属性，以及基于相对于所述像素块的重心差确定所述像素块内的相邻像素的属性参考像素被公开。用于计算待渲染对象的至少一个属性的电路包括：初始计算电路，响应于限定所述对象的至少一部分的像素块，提供全精度参考像素属性数据; 以及可操作地耦合到初始计算电路的导数电路，响应于像素块提供精确的相邻像素属性数据。导数电路包括多个像素属性子电路或分量，其以比用于定义参考像素的精度小的精度确定像素图块内的相邻像素的属性值。

10. 发明申请

US20090262864A1 SYMMETRICAL DATA SIGNAL PROCESSING 有权
标题翻译：对称数据信号处理
公开(公告)号：US20090262864A1
公开(公告)日：2009-10-22
申请号：US12465322
申请日：2009-05-13
申请人： Hong Liu , Raul A. Casas , Haosong FU
发明人： Hong Liu , Raul A. Casas , Haosong FU
IPC分类号： H03D3/00
CPC分类号： H04L25/03171 , H04L25/0212 , H04L27/04 , H04L2025/03382 , H04L2025/03522
摘要： In a digital communications receiver configured to receive, via a communications channel, a received first signal representing a sequence of symbols, each symbol being encoded to be representative of data bits, a method of processing the received signal includes adjusting a magnitude, filtering, and applying cyclic prefix restoration, to the received signal to produce a second signal, converting the second signal from time domain to frequency domain to produce a frequency domain signal, and determining a first quantity of values representing a first portion of the symbols by evaluating a relationship of channel values representing characteristics of the communications channel and a second quantity of values representing a portion of the frequency domain signal, the first quantity being smaller than the second quantity.
摘要翻译：在被配置为经由通信信道接收表示符号序列的每个符号被编码为表示数据比特的数字通信接收机中，处理接收信号的方法包括调整幅度，滤波和对所接收的信号应用循环前缀恢复以产生第二信号，将所述第二信号从时域转换到频域以产生频域信号，以及通过评估所述符号的关系来确定表示所述符号的第一部分的第一数量的值表示所述通信信道的特性的信道值和表示所述频域信号的一部分的第二数量值，所述第一数量小于所述第二数量。

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