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81. 发明授权

US08372710B2 Vertical transistors 有权
标题翻译：垂直晶体管
公开(公告)号：US08372710B2
公开(公告)日：2013-02-12
申请号：US13329977
申请日：2011-12-19
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/20
CPC分类号： H01L29/7827 , H01L27/1052 , H01L27/10823 , H01L27/10876 , H01L27/11 , H01L27/115 , H01L27/11517 , H01L29/66621 , H01L29/78
摘要： A semiconductor structure having U-shaped transistors includes source/drain regions at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. Methods of forming semiconductor structures are also disclosed.
摘要翻译：具有U形晶体管的半导体结构包括由衬底中的交叉沟槽限定的柱对的顶部的源/漏区域。一个支柱通过在周围的沟槽上方延伸的脊连接到一对中的另一个柱。柱的脊和下部在U形结构的相对侧限定U形通道，面对在那些相对侧上的沟槽中的栅极结构，形成双面环绕晶体管。可选地，一对柱之间的空间也用栅电极材料填充以限定三面环绕栅极晶体管。每对的源极/漏极区之一延伸到数字线，而另一个延伸到诸如电容器的存储器存储器件。还公开了形成半导体结构的方法。

82. 发明授权

US08367561B2 Method in depositing metal oxide materials 有权
标题翻译：沉积金属氧化物材料的方法
公开(公告)号：US08367561B2
公开(公告)日：2013-02-05
申请号：US12663782
申请日：2008-07-02
申请人： Jarmo Maula , Kari Harkonen
发明人： Jarmo Maula , Kari Harkonen
IPC分类号： H01L21/31 , H01L21/00 , H01L21/8242 , H01L21/469 , H01L21/44
CPC分类号： C23C16/45534 , C23C16/403 , C23C16/405
摘要： The present invention relates to a method for enhancing uniformity of metal oxide coatings formed by Atomic Layer Deposition (ALD) or ALD-type processes. Layers are formed using alternating pulses of metal halide and oxygen-containing precursors, preferably water, and purging when necessary. An introduction of modificator pulses following the pulses of the oxygen-containing precursor affects positively on layer uniformity, which commonly exhibits gradients, particularly in applications with closely arranged substrates. In particular, improvement in layer thickness uniformity is obtained. According to the invention, alcohols having one to three carbon atoms can be used as the modificator.
摘要翻译：本发明涉及一种增强由原子层沉积（ALD）或ALD型工艺形成的金属氧化物涂层的均匀性的方法。使用金属卤化物和含氧前体，优选水的交替脉冲形成层，并且在必要时进行清洗。在含氧前体的脉冲之后引入改性脉冲对层的均匀性产生积极影响，这通常表现出梯度，特别是在具有紧密排列的衬底的应用中。特别地，获得了层厚均匀性的改善。根据本发明，可以使用具有一至三个碳原子的醇作为改性剂。

83. 发明授权

US08362538B2 Memory device, semiconductor device, and electronic device 有权
公开(公告)号：US08362538B2
公开(公告)日：2013-01-29
申请号：US12976206
申请日：2010-12-22
申请人： Jun Koyama , Shunpei Yamazaki
发明人： Jun Koyama , Shunpei Yamazaki
IPC分类号： H01L27/108 , H01L21/8242 , H01L21/336
CPC分类号： H01L27/1225 , G06F1/206 , G11C11/412 , G11C27/024 , H01L21/84 , H01L27/0629 , H01L27/11517 , H01L27/1203 , H03K19/094 , H03K19/0948
摘要： An object is to provide a memory device which does not need a complex manufacturing process and whose power consumption can be suppressed, and a semiconductor device including the memory device. A solution is to provide a capacitor which holds data and a switching element which controls storing and releasing charge in the capacitor in a memory element. In the memory element, a phase-inversion element such as an inverter or a clocked inverter includes the phase of an input signal is inverted and the signal is output. For the switching element, a transistor including an oxide semiconductor in a channel formation region is used. In the case where application of a power supply voltage to the phase-inversion element is stopped, the data is stored in the capacitor, so that the data is held in the capacitor even when the application of the power supply voltage to the phase-inversion element is stopped.

84. 发明授权

US08329533B2 Stacked capacitor for double-poly flash memory 有权
标题翻译：双聚闪存的堆叠电容
公开(公告)号：US08329533B2
公开(公告)日：2012-12-11
申请号：US12781720
申请日：2010-05-17
申请人： Julian Chang , An-Xing Shen , Soon-Won Kang
发明人： Julian Chang , An-Xing Shen , Soon-Won Kang
IPC分类号： H01L21/8242
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11531 , H01L28/60 , H01L29/94
摘要： A stacked capacitor for double-poly flash memory is provided. The stacked capacitor is formed by a lower electrode, a lower dielectric layer, a central electrode, an upper dielectric layer, and an upper electrode, wherein the lower electrode is a doped region in a substrate. The manufacturing process of this stacked capacitor can be fully integrated in to the manufacturing process of the double-poly flash memory cell.
摘要翻译：提供了一种用于双聚焦闪存的叠层电容器。堆叠电容器由下电极，下电介质层，中心电极，上电介质层和上电极形成，其中下电极是衬底中的掺杂区域。该叠层电容器的制造过程可以完全集成到双聚光闪存单元的制造过程中。

85. 发明授权

US08324049B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08324049B2
公开(公告)日：2012-12-04
申请号：US12641073
申请日：2009-12-17
申请人： Jin-A Kim , Seok-Ho Jie
发明人： Jin-A Kim , Seok-Ho Jie
IPC分类号： H01L21/8242
CPC分类号： H01L27/10894 , H01L27/105 , H01L27/10852
摘要： A semiconductor device and a method for fabricating a semiconductor device are provided. The method for fabricating a semiconductor device includes forming an isolation layer over a semiconductor substrate defining first and second regions, etching the isolation layer at an edge of the first region to form a guard ring pattern, forming a buried guard ring filling the guard ring pattern, selectively etching the isolation layer of the first region to form a plurality of patterns, forming a plurality of conductive patterns in the respective patterns, and completely removing the isolation layer of the first region through a dip-out process.
摘要翻译：提供半导体器件和制造半导体器件的方法。制造半导体器件的方法包括在限定第一和第二区域的半导体衬底上形成隔离层，在第一区域的边缘蚀刻隔离层以形成保护环图案，形成填充保护环图案的掩埋保护环选择性地蚀刻第一区域的隔离层以形成多个图案，在各图案中形成多个导电图案，并且通过浸出工艺完全去除第一区域的隔离层。

86. 发明授权

US08313995B2 Method for manufacturing a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08313995B2
公开(公告)日：2012-11-20
申请号：US13005694
申请日：2011-01-13
申请人： Martin Poelzl
发明人： Martin Poelzl
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L29/7813 , H01L29/0878 , H01L29/407 , H01L29/42368 , H01L29/66734 , H01L29/7397 , H01L29/7811
摘要： A method for forming a semiconductor device is provided. The method includes providing a semiconductor body with a horizontal surface. An epitaxy hard mask is formed on the horizontal surface. An epitaxial region is formed by selective epitaxy on the horizontal surface relative to the epitaxy hard mask so that the epitaxial region is adjusted to the epitaxy hard mask. A vertical trench is formed in the semiconductor body. An insulated field plate is formed in a lower portion of the vertical trench and an insulated gate electrode is formed above the insulated field plate. Further, a method for forming a field-effect semiconductor device is provided.
摘要翻译：提供一种形成半导体器件的方法。该方法包括提供具有水平表面的半导体本体。在水平面上形成外延硬掩模。通过在水平表面上相对于外延硬掩模的选择性外延形成外延区域，使得外延区域被调整到外延硬掩模。在半导体本体中形成垂直沟槽。绝缘场板形成在垂直沟槽的下部，绝缘栅电极形成在绝缘场板的上方。此外，提供了一种用于形成场效应半导体器件的方法。

87. 发明授权

US08309416B2 Semiconductor device with buried bit lines interconnected to one-side-contact and fabrication method thereof 有权
标题翻译：具有与一侧接触互连的埋入位线的半导体器件及其制造方法
公开(公告)号：US08309416B2
公开(公告)日：2012-11-13
申请号：US12649684
申请日：2009-12-30
申请人： Eun-Shil Park , Yong-Seok Eun , Kee-Jeung Lee , Min-Soo Kim
发明人： Eun-Shil Park , Yong-Seok Eun , Kee-Jeung Lee , Min-Soo Kim
IPC分类号： H01L21/8242
CPC分类号： H01L27/10885 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with reduced resistance of a buried bit line, and a method for fabricating the same. The method for fabricating a semiconductor device includes etching a semiconductor substrate to form a plurality of active regions which are separated from one another by trenches formed in between, forming a side contact on a sidewall of each active region, and forming metal bit lines, each filling a portion of a respective trench and connected to the side contact.
摘要翻译：具有降低的掩埋位线电阻的半导体器件及其制造方法。半导体器件的制造方法包括蚀刻半导体衬底以形成多个有源区，它们之间形成沟槽，在每个有源区的侧壁上形成侧接触，并形成金属位线填充相应沟槽的一部分并连接到侧触点。

88. 发明申请

US20120273862A1 SEMICONDUCTOR APPARATUS WITH MULTIPLE TIERS, AND METHODS 有权
标题翻译：具有多个层次的半导体器件和方法
公开(公告)号：US20120273862A1
公开(公告)日：2012-11-01
申请号：US13096822
申请日：2011-04-28
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/11582 , G11C8/10 , H01L21/02164 , H01L21/02532 , H01L21/02595 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L29/495 , H01L29/4966
摘要： Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.
摘要翻译：公开了装置和方法，包括包括多个第一半导体材料层的装置，每个层包括至少一个存储单元的至少一个存取线和至少一个至少一个的至少一个源极，沟道和/或漏极外围晶体管，例如在接入线解码器电路或数据线复用电路中使用的晶体管。该装置还可以包括延伸穿过第一半导体材料层的第二半导体材料的多个支柱，每个支柱包括至少一个存储器单元的源极，沟道和/或漏极，或者在至少一个外围晶体管。还描述了形成这种装置的方法以及其他实施例。

89. 发明授权

US08298885B2 Semiconductor device comprising metal gates and a silicon containing resistor formed on an isolation structure 有权
标题翻译：半导体器件包括金属栅极和形成在隔离结构上的含硅电阻器
公开(公告)号：US08298885B2
公开(公告)日：2012-10-30
申请号：US12759785
申请日：2010-04-14
申请人： Andy Wei , Andrew Waite
发明人： Andy Wei , Andrew Waite
IPC分类号： H01L21/8242
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823842 , H01L27/0629 , H01L28/20
摘要： In a semiconductor device comprising sophisticated high-k metal gate structures formed in accordance with a replacement gate approach, semiconductor-based resistors may be formed above isolation structures substantially without being influenced by the replacement gate approach. Consequently, enhanced area efficiency may be achieved compared to conventional strategies, in which the resistive structures may have to be provided on the basis of a gate electrode metal, while, nevertheless, a low parasitic capacitance may be accomplished due to providing the resistive structures above the isolation structure.
摘要翻译：在包括根据替换栅极方法形成的复杂的高k金属栅极结构的半导体器件中，半导体基电阻器可以基本上不受更换栅极方法的影响而形成在隔离结构之上。因此，与常规策略相比，可以实现增强的面积效率，其中电阻结构可能必须基于栅电极金属提供，而尽管如此，可以通过提供上述电阻结构来实现低寄生电容隔离结构。

90. 发明授权

US08283227B2 Method for manufacturing semiconductor memory device 有权
标题翻译：制造半导体存储器件的方法
公开(公告)号：US08283227B2
公开(公告)日：2012-10-09
申请号：US13282814
申请日：2011-10-27
申请人： Toshiyuki Hirota , Takakazu Kiyomura
发明人： Toshiyuki Hirota , Takakazu Kiyomura
IPC分类号： H01L21/8242
CPC分类号： H01L27/10817 , H01L27/10852 , H01L28/57
摘要： In a method for manufacturing a semiconductor memory device, a three dimensional lower electrode including a titanium nitride film is formed on a semiconductor substrate, and a dielectric film is formed on the surface of the lower electrode. After a first upper electrode is formed at a temperature that the crystal of the dielectric film is not grown on the surface of the dielectric film, the first upper electrode and the dielectric film are heat-treated at a temperature that the crystal of the dielectric film is grown to convert at least a portion of the dielectric film into a crystalline state. Thereafter, a second upper electrode is formed on the surface of the first upper electrode.
摘要翻译：在制造半导体存储器件的方法中，在半导体衬底上形成包括氮化钛膜的三维下电极，并且在下电极的表面上形成电介质膜。在电介质膜的晶体不在电介质膜的表面上生长的温度下形成第一上电极之后，在电介质膜的晶体的温度下对第一上电极和电介质膜进行热处理生长以将至少一部分电介质膜转化为结晶状态。此后，在第一上电极的表面上形成第二上电极。

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