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81. 发明申请

US20050275674A1 GENERAL SERIAL INTERFACE SYSTEM 失效
标题翻译：一般串行接口系统
公开(公告)号：US20050275674A1
公开(公告)日：2005-12-15
申请号：US10908632
申请日：2005-05-19
申请人： Hao-Feng Hung
发明人： Hao-Feng Hung
IPC分类号： B41J29/38 , G06F3/00 , G06F3/12 , G06F13/00 , G06F13/12 , G06F13/42 , G11C5/00
CPC分类号： G06F13/4291
摘要： A serial transmission control system accesses data based on status signal, includes a timing register for storing a predetermined times of a basic period width and a predetermined number of trigger times, a data buffer for storing data, a timing control state machine for outputting the status signal until receiving a terminal signal. The status signals have a period width complying with the predetermined time of the basic period width. While the terminal signal is received and a number of outputting the status signals does not comply with the predetermined number of trigger times, the status signal will keep outputting until complying with the predetermined number of trigger times. A transforming circuit is for accessing the data stored in the data buffer.
摘要翻译：串行传输控制系统基于状态信号访问数据，包括用于存储基本周期宽度和预定数量的触发时间的预定次数的定时寄存器，用于存储数据的数据缓冲器，用于输出状态的定时控制状态机信号直到接收到终端信号。状态信号具有符合基本周期宽度的预定时间的周期宽度。当接收到终端信号并且输出状态信号的数量不符合预定数量的触发时间时，状态信号将保持输出，直到符合预定数量的触发时间。变换电路用于访问存储在数据缓冲器中的数据。

82. 发明授权

US06975558B2 Integrated circuit device 失效
标题翻译：集成电路器件
公开(公告)号：US06975558B2
公开(公告)日：2005-12-13
申请号：US10939500
申请日：2004-09-14
申请人： Michael Farmwald , Mark Horowitz
发明人： Michael Farmwald , Mark Horowitz
IPC分类号： G06F1/10 , G06F11/00 , G06F11/10 , G06F12/00 , G06F12/02 , G06F12/06 , G06F13/16 , G06F13/376 , G11C5/00 , G11C5/06 , G11C7/10 , G11C7/22 , G11C8/00 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/409 , G11C11/4096 , G11C29/00
CPC分类号： G11C7/1066 , G06F11/006 , G06F11/1048 , G06F12/0215 , G06F12/0661 , G06F12/0684 , G06F13/1605 , G06F13/161 , G06F13/1678 , G06F13/1689 , G06F13/1694 , G06F13/376 , G06F13/4239 , G11C5/00 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/066 , G11C7/1006 , G11C7/1012 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1069 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/22 , G11C7/222 , G11C7/225 , G11C8/00 , G11C11/4076 , G11C11/4096 , G11C29/88 , G11C2207/105 , G11C2207/108 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An integrated circuit device is disclosed. In one particular exemplary embodiment, the integrated circuit device may comprise a first circuit to receive, in a multiplexed format, control information and address information, wherein the control information specifies a write operation and the address information specifies a location within a memory array for the write operation. The integrated circuit device may also comprise a second circuit that includes a plurality of output drivers to output write data to be written to the memory array during the write operation, wherein the write data is output after a number of clock cycles of an external clock signal transpire, wherein the write data is output in response to the control information, and wherein each output driver of the plurality of output drivers outputs two bits of the write data during a single clock cycle of the external clock signal.
摘要翻译：公开了一种集成电路器件。在一个特定示例性实施例中，集成电路设备可以包括以多路复用格式接收控制信息和地址信息的第一电路，其中控制信息指定写入操作，并且地址信息指定用于存储器阵列的存储器阵列内的位置写操作。集成电路器件还可以包括第二电路，其包括多个输出驱动器以在写入操作期间输出要写入存储器阵列的写入数据，其中写入数据在外部时钟信号的多个时钟周期之后被输出其中写入数据是响应控制信息输出的，并且其中多个输出驱动器的每个输出驱动器在外部时钟信号的单个时钟周期内输出写数据的两位。

83. 发明申请

US20050270858A1 Plural circuit selection using role reversing control inputs 有权
公开(公告)号：US20050270858A1
公开(公告)日：2005-12-08
申请号：US11198064
申请日：2005-08-05
申请人： Lee Whetsel
发明人： Lee Whetsel
IPC分类号： G01R31/3185 , G06F1/04 , G11C5/00 , H04J3/06 , H04L7/00
CPC分类号： G06F13/4291 , G01R31/31725 , G01R31/31726 , G01R31/318536 , G01R31/318594 , G06F1/04 , G06F1/06 , H04B1/18 , H04J3/0644 , H04L7/0008
摘要： Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

84. 发明申请

US20050270853A1 Memory module and method for accessing the same 审中-公开
标题翻译：内存模块和访问方法
公开(公告)号：US20050270853A1
公开(公告)日：2005-12-08
申请号：US10860142
申请日：2004-06-04
申请人： Kevin Chiang , Chih-Chen Tsai
发明人： Kevin Chiang , Chih-Chen Tsai
IPC分类号： G11C5/00 , G11C7/10 , G11C7/22
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1066 , G11C7/22
摘要： A memory module and a method for accessing the same are proposed. The memory module comprises a memory, a transmission selection port connected to input of the memory, a first data output port and a second data output port connected to output of the memory. The transmission selection port input one of a first address signal and a second address signal to the memory according to a logical level of a first clock signal. The first data output port and the second data output port access data of memory designated by the first address signal or the second address signal according to the logical level of the first clock signal.
摘要翻译：提出了一种存储器模块及其访问方法。存储器模块包括存储器，连接到存储器的输入的传输选择端口，连接到存储器的输出的第一数据输出端口和第二数据输出端口。传输选择端口根据第一时钟信号的逻辑电平将一个第一地址信号和第二地址信号输入到存储器。第一数据输出端口和第二数据输出端口根据第一时钟信号的逻辑电平访问由第一地址信号或第二地址信号指定的存储器的数据。

85. 发明申请

US20050268774A1 FREQUENCY SPECTRUM CONVERSION TO NATURAL HARMONIC FREQUENCIES PROCESS 有权
标题翻译：频率频谱转换为自然和谐频率过程
公开(公告)号：US20050268774A1
公开(公告)日：2005-12-08
申请号：US10908972
申请日：2005-06-02
申请人： Alan Howarth , Wesley Bateman
发明人： Alan Howarth , Wesley Bateman
IPC分类号： G09B15/02 , G10H1/44 , G10H7/00 , G11C5/00
CPC分类号： G10H1/44 , G09B15/00 , G10H1/02 , G10H2210/066 , G10H2210/395
摘要： A process for converting standard musical notes to Ra format musical notes comprising inputting a signal of standard musical notes, analyzing the frequency of each note in the signal, selecting a Ra format natural harmonic resonance, converting the frequency of each note in the signal to a Ra format frequency corresponding to the selected Ra format natural harmonic resonance, and outputting a signal consisting of the converted notes. A apparatus including a processor capable of performing the inventive process on a signal of standard musical notes. The apparatus including a signal input port and a signal output port, means for converting the frequency of standard musical notes to a corresponding frequency of Ra musical notes, means for selecting a Ra format natural harmonic resonance, and a frequency analyzer.
摘要翻译：一种用于将标准音符转换为Ra格式音符的过程，包括输入标准音符信号，分析信号中每个音符的频率，选择Ra格式的自然谐波共振，将该信号中每个音符的频率转换为 Ra格式频率对应于所选择的Ra格式的自然谐波共振，并输出由转换的音符组成的信号。一种包括能够对标准音符的信号执行创造性处理的处理器的装置。所述装置包括信号输入端口和信号输出端口，用于将标准音符的频率转换为Ra音符的对应频率的装置，用于选择Ra格式的自然谐波谐振的装置和频率分析器。

86. 发明申请

US20050265083A1 Method and system for monitoring a supply-chain 审中-公开
标题翻译：监控供应链的方法和系统
公开(公告)号：US20050265083A1
公开(公告)日：2005-12-01
申请号：US11176585
申请日：2005-07-07
申请人： Brain Perry
发明人： Brain Perry
IPC分类号： G06Q10/00 , G11C5/00
CPC分类号： G06Q10/087 , G06Q10/06
摘要： A method of monitoring supply chain activity throughout a plurality of supply chain sites includes extracting, at each supply chain site, supply-related data to be monitored. The data is maintained in plural formats at the supply chain sites, and translated the data to a common format. The extracted data is then uploaded to and collected, from each supply chain site, to a data collection center or site. Upon a user request, a portion of the collected data is formatted, at the data collection site, into one of a plurality of views, responsive to criteria selected by the user, for presentation to the user, the portion of formatted data being dependent on access rights granted to the user's supply chain site. Finally, the formatted data view is published to the user's supply chain site. The data collection center comprises a data collector in which the uploaded data is stored, and a publisher for publishing data from the data collector upon request. Each supply chain site has a data storage device for maintaining its own supply-chain data, a data transfer engine (DTE), for transferring the supply-chain data to the data collection center, input means for allowing a user to query the data collector, and a display for displaying data published by the publisher in response to a query. The inbound data received from the multiple supply chain sites is monitored at the data collection site. If a problem condition is detected, such as a forecasted or present shortage or surplus, an alert is asserted, for example, by highlighting an Alert indicator, such as an Alert tab, on a user screen. Upon selection of the highlighted Alert indicator by a user, details of the detected problem condition are displayed.
摘要翻译：监测多个供应链站点内的供应链活动的方法包括在每个供应链站点提取要监视的供应相关数据。数据在供应链站点以多种格式保存，并将数据转换为通用格式。提取的数据然后从每个供应链站点上传到并收集到数据收集中心或站点。在用户请求时，响应于由用户选择的标准将所收集的数据的一部分在数据收集站点格式化成多个视图之一，以呈现给用户，格式化数据的部分依赖于授予用户供应链网站的访问权限。最后，将格式化的数据视图发布到用户的供应链站点。数据收集中心包括存储上传数据的数据收集器，以及根据请求从数据收集器发布数据的发布者。每个供应链站点都具有用于维护其自己的供应链数据的数据存储设备，用于将供应链数据传送到数据收集中心的数据传输引擎（DTE），用于允许用户查询数据收集器的输入装置以及显示器，用于显示发布者响应于查询而发布的数据。从多个供应链站点收到的入站数据在数据收集站点进行监控。如果检测到问题状况（例如预测或缺少或过剩），则例如通过在用户屏幕上突出显示警报指示符（例如警报标签）来警告警报。当用户选择突出显示的警报指示符时，显示检测到的问题状况的细节。

87. 发明授权

US06971032B2 Supplying multiple voltages via three power supply terminals to a semiconductor device that is connectable to a host device and a peripheral device 有权
标题翻译：通过三个电源端子将多个电压提供给可连接到主机设备和外围设备的半导体器件
公开(公告)号：US06971032B2
公开(公告)日：2005-11-29
申请号：US09946512
申请日：2001-09-06
申请人： Mitsuya Ohie , Kyotaro Nakamura , Shuichi Hashidate
发明人： Mitsuya Ohie , Kyotaro Nakamura , Shuichi Hashidate
IPC分类号： H01L27/04 , G06F1/26 , G06F13/38 , G11C5/00 , H01L21/822
CPC分类号： G06F1/32 , G06F13/385 , G06F2213/0042 , Y02D10/14 , Y02D10/151
摘要： A semiconductor device includes first through third power supply terminals respectively supplied with first, second and third power supply voltages. The semiconductor device also includes a first terminal connectable to a host device, and a second terminal connectable to a peripheral device. A first circuit block is connected to the first terminal and the first power supply terminal, and receives data output from the host device based on the first power supply voltage. A second circuit block is connected to the second terminal and the third power supply terminal, and receives data output from the peripheral device based on the third power supply voltage. A third circuit block is connected to the second power supply terminal, and controls operation of the first circuit block and the second circuit block based on the second power supply voltage.
摘要翻译：半导体器件包括分别提供有第一，第二和第三电源电压的第一至第三电源端子。半导体器件还包括可连接到主机设备的第一终端和可连接到外围设备的第二终端。第一电路块连接到第一端子和第一电源端子，并且基于第一电源电压接收从主机设备输出的数据。第二电路块连接到第二端子和第三电源端子，并且基于第三电源电压接收从外围设备输出的数据。第三电路块连接到第二电源端子，并且基于第二电源电压来控制第一电路块和第二电路块的操作。

88. 发明申请

US20050262388A1 Memory controllers with interleaved mirrored memory modes 有权
标题翻译：具有交错镜像存储器模式的存储器控制器
公开(公告)号：US20050262388A1
公开(公告)日：2005-11-24
申请号：US11181583
申请日：2005-07-14
申请人： Eric Dahlen , Warren Morrow , Peter Vogt
发明人： Eric Dahlen , Warren Morrow , Peter Vogt
IPC分类号： G06F11/20 , G06F12/00 , G06F12/02 , G06F12/12 , G06F12/16 , G11C5/00 , G11C29/00
CPC分类号： G06F11/2061 , G06F11/2069 , G06F11/2087 , G11C8/04
摘要： In some embodiments, a memory controller includes first and second memory channel interfaces and memory access control circuitry. The memory access control circuitry is to send first and second primary data sections to the first and second memory channel interfaces, respectively, and send first and second redundant data sections to the second and first memory channel interfaces, respectively. The first and second redundant data sections are redundant with respect to the first and second primary data sections, respectively. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，存储器控制器包括第一和第二存储器通道接口和存储器访问控制电路。存储器访问控制电路分别将第一和第二主数据段发送到第一和第二存储器通道接口，并且分别向第二和第一存储器通道接口发送第一和第二冗余数据段。第一和第二冗余数据部分分别相对于第一和第二主数据部分是冗余的。描述和要求保护其他实施例。

89. 发明申请

US20050259496A1 Throttling memory in a computer system 有权
标题翻译：在计算机系统中调节内存
公开(公告)号：US20050259496A1
公开(公告)日：2005-11-24
申请号：US10852923
申请日：2004-05-24
申请人： Pochang Hsu , Animesh Mishra , Jun Shi
发明人： Pochang Hsu , Animesh Mishra , Jun Shi
IPC分类号： G06F1/20 , G06F1/32 , G06F13/16 , G11C5/00 , G11C7/04
CPC分类号： G01K13/00 , G06F1/206 , G06F1/3203 , G06F13/16 , G11C5/04 , G11C5/143 , G11C7/04 , Y02D10/16
摘要： Systems and methods of managing memory devices provide for reduced power consumption and better thermal management through enhanced memory throttling. In one embodiment a memory unit includes a memory device and a temperature measurement module coupled to the memory device. The temperature measurement device measures the internal temperature of the memory device. Memory throttling can therefore be implemented based on more accurate measurements and with a much shorter response time.
摘要翻译：管理存储器件的系统和方法通过增强的存储器节流来提供降低的功耗和更好的热管理。在一个实施例中，存储器单元包括耦合到存储器件的存储器件和温度测量模块。温度测量装置测量存储器件的内部温度。因此，可以基于更准确的测量并且具有短得多的响应时间来实现内存限制。

90. 发明申请

US20050254219A1 Memory card 有权
公开(公告)号：US20050254219A1
公开(公告)日：2005-11-17
申请号：US11182959
申请日：2005-07-15
申请人： Seiji Nakanishi , Takashi Torii , Noriaki Furuta , Takahiro Sakamoto , Masayoshi Yano
发明人： Seiji Nakanishi , Takashi Torii , Noriaki Furuta , Takahiro Sakamoto , Masayoshi Yano
IPC分类号： G06K19/073 , G06K19/077 , G11C5/00 , H05K1/14
CPC分类号： G06K19/07743 , G06K19/073 , G06K19/07732 , Y10S439/945 , Y10S439/946
摘要： A memory card includes: a main body of the memory card in which a notched section is formed; a semiconductor memory; and a write/nonwrite setting element for setting the write/nonwrite state of data in the semiconductor memory, the write/nonwrite setting element being slidably fitted in the notched section, wherein the main body of the memory card includes an upper main body and a lower main body; at least one of the upper main body and the lower main body has an elastic guide formed within the notched section; the write/nonwrite setting element slides along the elastic guide so as to set the write/nonwrite state of the data in the semiconductor memory; and the elastic guide has an engagement portion for engagedly stopping the write/nonwrite setting element so as to select the position of the write/nonwrite setting element with respect to the elastic guide.

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