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81. 发明授权

US4377757A Logic module for integrated digital circuits 失效
标题翻译：集成数字电路逻辑模块
公开(公告)号：US4377757A
公开(公告)日：1983-03-22
申请号：US120070
申请日：1980-02-11
申请人： Bernd Konemann , Joachim Mucha , Gunther Zwiehoff
发明人： Bernd Konemann , Joachim Mucha , Gunther Zwiehoff
IPC分类号： G01R31/3181 , H03K3/335 , H03K21/00
CPC分类号： G01R31/31813
摘要： A logic module is disclosed for construction in an integrated digital circuit for promoting testing of the integrated circuit. A latch module is provided for functioning as a latch, as a back-coupled shift register, and in one embodiment of the invention as a linear shift register. The latch module is formed of a plurality of basic cells each of which has a flip-flop with associated logic gates, one of which is an exclusive OR gate. The latch module also has an input, parallel data inputs and parallel data data outputs. For functioning in the back-coupling mode, an exclusive OR gate is connected between at least one of the flip-flops and the input to the latch module.
摘要翻译：公开了用于在集成数字电路中构建用于促进集成电路的测试的逻辑模块。提供了一个闩锁模块，用作作为反向耦合移位寄存器的锁存器，并且在本发明的一个实施例中用作线性移位寄存器。锁存模块由多个基本单元形成，每个基本单元具有一个具有相关逻辑门的触发器，其中一个是异或门。锁存模块还具有输入，并行数据输入和并行数据数据输出。为了在反向耦合模式下工作，异或门连接在至少一个触发器和到锁存模块的输入端。

82. 发明授权

US11994557B2 Adaptive port ceiling assignment for background I/O operations between heterogeneous storage arrays 有权
公开(公告)号：US11994557B2
公开(公告)日：2024-05-28
申请号：US17943244
申请日：2022-09-13
申请人： Dell Products, L.P.
发明人： Ananthakrishnan Anirudhan , Santoshkumar Konnur , Deepak Vokaliga
IPC分类号： G01R31/317 , G01R31/3181
CPC分类号： G01R31/31715 , G01R31/31725 , G01R31/31813
摘要： A port manager is configured to implement adaptive port ceiling assignment for background Input/Output (I/O) operations between heterogeneous storage arrays. The port manager generates a set of test I/O operations, applies the I/O operations to a port under test, determines a response time to complete the I/O operations on the port under test, and compares the response time of the current test with response times of a set of previous tests. Based on the test values, the port manager identifies a throughput inflection point for the port under test, which is used to set a maximum throughput of the port under test. The adaptive ceiling for the port under test is then set based on the maximum throughput times a ceiling percentage threshold value. The determined adaptive ceiling value is then used to prospectively limit background I/O operations on the port under test.

83. 发明公开

US20240085474A1 Adaptive Port Ceiling Assignment for Background I/O Operations Between Heterogeneous Storage Arrays 审中-公开
公开(公告)号：US20240085474A1
公开(公告)日：2024-03-14
申请号：US17943244
申请日：2022-09-13
申请人： Dell Products, L.P.
发明人： Ananthakrishnan Anirudhan , Santoshkumar Konnur , Deepak Vokaliga
IPC分类号： G01R31/317 , G01R31/3181
CPC分类号： G01R31/31715 , G01R31/31725 , G01R31/31813
摘要： A port manager is configured to implement adaptive port ceiling assignment for background Input/Output (I/O) operations between heterogeneous storage arrays. The port manager generates a set of test I/O operations, applies the I/O operations to a port under test, determines a response time to complete the I/O operations on the port under test, and compares the response time of the current test with response times of a set of previous tests. Based on the test values, the port manager identifies a throughput inflection point for the port under test, which is used to set a maximum throughput of the port under test. The adaptive ceiling for the port under test is then set based on the maximum throughput times a ceiling percentage threshold value. The determined adaptive ceiling value is then used to prospectively limit background I/O operations on the port under test.

84. 发明授权

US11867760B2 Parameter setting method and apparatus, system, and storage medium 有权
公开(公告)号：US11867760B2
公开(公告)日：2024-01-09
申请号：US17442263
申请日：2021-06-17
申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.
发明人： Hao He
IPC分类号： G11C7/00 , G01R31/3181 , G01R31/28 , G01R31/3183
CPC分类号： G01R31/31813 , G01R31/2889 , G01R31/318314
摘要： The present application provides a parameter setting method and apparatus, a system, and a storage medium. The parameter setting method includes: obtaining first setting values of multiple memory parameters and storage locations of the multiple memory parameters in a non-volatile memory; generating a first parameter setting instruction according to the first setting value and the storage location of each memory parameter; and sending the first parameter setting instruction to a test device, so that the test device sets the memory parameter stored at the storage location in the non-volatile memory as the first setting value.

85. 发明授权

US11815554B2 Identifying data valid windows 有权
公开(公告)号：US11815554B2
公开(公告)日：2023-11-14
申请号：US17153726
申请日：2021-01-20
申请人： Micron Technology, Inc.
发明人： Phillip A. Rasmussen , Christopher D. Gagliano
IPC分类号： G01R31/3177 , G01R31/317 , G01R31/319 , G01R31/3181 , G01R31/30 , G06F11/26 , G06F11/22
CPC分类号： G01R31/3177 , G01R31/3004 , G01R31/31708 , G01R31/31711 , G01R31/31724 , G01R31/31725 , G01R31/31813 , G01R31/31924 , G06F11/2205 , G06F11/26
摘要： A tester including an interface configured to interface with an electronic device and a logic circuit. The logic circuit includes a pattern generator and at least one finite-state machine and is configured to sequentially acquire read data from the electronic device at sequential testing points of a testing range for evaluating an operating parameter of the electronic device or the tester until a set of consecutive passing points having a first passing point and a last passing point is identified, in response to identifying the first passing point, write data within the logic circuit of the tester identifying the first passing point, in response to identifying the last passing point, write data within the logic circuit of the tester identifying the last passing point, and output only data identifying the first passing point and data identifying the last passing point to a software application.

86. 发明授权

US11699502B2 Simulating memory cell sensing for testing sensing circuitry 有权
公开(公告)号：US11699502B2
公开(公告)日：2023-07-11
申请号：US17550352
申请日：2021-12-14
申请人： SanDisk Technologies LLC
发明人： Iris Lu , Yan Li , Ohwon Kwon
IPC分类号： G01R31/3181 , G11C29/16 , G11C7/06 , G11C29/54 , H10B80/00 , G01R31/3177 , H01L25/065 , H01L25/18
CPC分类号： G11C29/54 , G01R31/3181 , G11C7/065 , G11C7/067 , G11C29/16 , H10B80/00 , G01R31/3177 , H01L25/065 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/18
摘要： Technology is disclosed herein for testing circuitry that controls memory operations in a memory structure having non-volatile memory cells. The testing of the circuitry can be performed without the memory structure. The memory structure may reside on one semiconductor die, with sense blocks and a control circuit on another semiconductor die. The control circuit is able to perform die level control of memory operations in the memory structure. The control circuit may control the sense blocks to simulate sensing of non-volatile memory cells in the memory structure even though the sense blocks are not connected to the memory structure. The control circuit verifies correct operation of the semiconductor die based on the simulated sensing. For example, the control circuit may verify correct operation of a state machine that controls sense operations at a die level. Thus, the operation of the semiconductor die may be tested without the memory structure.

87. 发明授权

US11686772B2 Self diagnostic apparatus for electronic device 有权
公开(公告)号：US11686772B2
公开(公告)日：2023-06-27
申请号：US17496110
申请日：2021-10-07
申请人： PhosPhil Inc.
发明人： Byung Kyu Kim , Byeong Yun Kim
IPC分类号： G01R31/319 , G01R31/28 , G01R31/3185 , G01R31/327 , G01R31/3181 , G01R31/3187
CPC分类号： G01R31/31905 , G01R31/2891 , G01R31/3181 , G01R31/3187 , G01R31/31917 , G01R31/318566 , G01R31/3274
摘要： The present invention relates to a self-diagnostic apparatus capable of improving safety of a device under test (DUT) by analyzing a characteristic change of a DUT, such as a semiconductor, a circuit module, or a system, in a safe operating region over time and allowing a regular test and a periodic test to be performed even while the DUT is running.

88. 发明申请

US20220365136A1 METHOD AND SYSTEM FOR EFFICIENT TESTING OF DIGITAL INTEGRATED CIRCUITS 有权
公开(公告)号：US20220365136A1
公开(公告)日：2022-11-17
申请号：US17319835
申请日：2021-05-13
申请人： Palo Alto Research Center Incorporated
发明人： Aleksandar B. Feldman , Johan de Kleer , Alexandre Campos Perez , Ion Matei
IPC分类号： G01R31/3183 , G01R31/3181
摘要： One embodiment provides a method and a system for generating test vectors for testing a computational system. During operation, the system obtains a design of the computational system, the design comprising an original system. The system generates a design of a fault-augmented system block by adding a plurality of fault-emulating subsystems to the original system; generates a design of an equivalence-checking system based on the original system and the fault-augmented system block; encodes the design of the equivalence-checking system into a logic formula, with variables within the logic formula comprising inputs and outputs of the original system and inputs and outputs of the fault-augmented system block; and solves the logic formula to obtain a test vector used for testing at least one fault in the computational system.

89. 发明授权

US11494537B1 Method and system for efficient testing of digital integrated circuits 有权
公开(公告)号：US11494537B1
公开(公告)日：2022-11-08
申请号：US17319835
申请日：2021-05-13
申请人： Palo Alto Research Center Incorporated
发明人： Aleksandar B. Feldman , Johan de Kleer , Alexandre Campos Perez , Ion Matei
IPC分类号： G06F30/33 , G06F30/30 , G06F30/398 , G06F30/3308 , G06F30/367 , G01R31/00 , G01R31/28 , G01R31/3183 , G01R31/3181 , G06F30/3323 , G06F11/00
摘要： One embodiment provides a method and a system for generating test vectors for testing a computational system. During operation, the system obtains a design of the computational system, the design comprising an original system. The system generates a design of a fault-augmented system block by adding a plurality of fault-emulating subsystems to the original system; generates a design of an equivalence-checking system based on the original system and the fault-augmented system block; encodes the design of the equivalence-checking system into a logic formula, with variables within the logic formula comprising inputs and outputs of the original system and inputs and outputs of the fault-augmented system block; and solves the logic formula to obtain a test vector used for testing at least one fault in the computational system.

90. 发明授权

US11435733B2 Method and system to assure monitoring system validity 有权
公开(公告)号：US11435733B2
公开(公告)日：2022-09-06
申请号：US16183798
申请日：2018-11-08
申请人： Shlomo Berkovitch , Yaron Kaufmann
发明人： Shlomo Berkovitch , Yaron Kaufmann
IPC分类号： G05B23/02 , G01R31/3181 , G01R31/3183 , G06F11/263
摘要： There may be provided a method for validating a monitoring system, the method may include sensing, by at least one sensing element of the monitoring system, a physical parameter; sending sensed information that is related to the physical parameter to a remote computerized system of the monitoring system; applying, by the remote computerized system, a process on the sensed information to provide a response to the sensed information; generating validation information by a generator of the monitoring system; sending the validation information to the remote computerized system; applying, by the remote computerized system, the process on the validation information to provide a response to the validation information; and determining, by a validator of the monitoring system, a validity of the monitoring system based on the response to the validation result.

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