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    • 83. 发明授权
      US6157234A Pulse signal output circuit 有权
    • Pulse signal output circuit
    • 脉冲信号输出电路
    • US6157234A
    • 2000-12-05
    • US233103
    • 1999-01-19
    • Hiroshi Yamaguchi
    • Hiroshi Yamaguchi
    • H03K5/04 , H03K5/13 , H03K5/131 , H03K5/151 , H03K5/156 , H03H11/26
    • H03K5/1565
    • An integrated circuit has a first circuit which receives an input signal and outputs a first output signal, wherein the first output signal is produced by changing the pulse width of the input signal, a second circuit which receives the first output signal and outputs a second output signal, wherein the second output signal is produced by delaying the first output signal and a control circuit. The control circuit has a first control circuit which receives the first and second output signals and controls the first circuit based on the first and second output signals and a second control circuit which receives the first and second output signals and controls the second based on the first and second output signals.
    • 集成电路具有接收输入信号并输出​​第一输出信号的第一电路，其中通过改变输入信号的脉冲宽度来产生第一输出信号;第二电路，接收第一输出信号并输出​​第二输出 信号，其中通过延迟所述第一输出信号和控制电路来产生所述第二输出信号。 控制电路具有第一控制电路，其接收第一和第二输出信号并且基于第一和第二输出信号控制第一电路;以及第二控制电路，其接收第一和第二输出信号并基于第一输出信号控制第二输出信号 和第二输出信号。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 85. 发明授权
      US6104225A Semiconductor device using complementary clock and signal input state detection circuit used for the same 失效
    • Semiconductor device using complementary clock and signal input state detection circuit used for the same
    • 半导体器件采用互补时钟和信号输入状态检测电路相同
    • US6104225A
    • 2000-08-15
    • US76810
    • 1998-05-13
    • Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
    • Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
    • G11C7/22 , H03K5/00 , H03K5/135 , H03K5/151 , H03L7/081 , G06F1/04
    • H03L7/0805 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/135 , H03K5/151 , H03K2005/00234 , H03L7/0814
    • A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180.degree. phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A 1/2 phase clock generating circuit generates a 1/2 phase shift signal 180.degree. out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the 1/2 phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.
    • 公开了一种半导体器件，用于从外部时钟产生彼此互补的第一和第二内部时钟，并且可用于使用互补时钟的系统和内部产生180°相位时钟的系统的系统。 第一时钟输入电路（缓冲器）被提供有第一外部时钟并输出第一内部时钟。 第二时钟输入电路（缓冲器）被提供有与第一外部时钟互补的第二外部时钟并输出第二时钟。 A + E，fra 1/2 + EE相位时钟发生电路产生与第一内部时钟异相180°的+ E，fra 1/2 + EE相移信号。 第二外部时钟状态检测电路判断第二外部时钟是否被输入到第二时钟输入缓冲器。 当第二外部时钟被输入时，开关被操作以产生第二时钟作为第二内部时钟，并且当第二外部时钟未被输入时产生+ E，fra 1/2 + EE相移信号作为第二内部时钟 ，根据第二外部时钟状态检测电路的判断。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 88. 发明授权
      US5952863A Circuit and method for generating non-overlapping clock signals for an integrated circuit 失效
    • Circuit and method for generating non-overlapping clock signals for an integrated circuit
    • 用于为集成电路产生非重叠时钟信号的电路和方法
    • US5952863A
    • 1999-09-14
    • US762169
    • 1996-12-09
    • Jason A.T. Jones , Gary L. Swoboda
    • Jason A.T. Jones , Gary L. Swoboda
    • G06F1/06 , H03K5/151 , H03K5/19 , H03K5/15
    • H03K5/1515
    • A method is provided for forming non-overlapping clock signals 402 and 404 for an integrated circuit. A reference clock 300 whose frequency is twice that of a desired operating frequency for the integrated circuit is used. A master clock signal is formed which has a high pulse width T9a which is approximately the same as the high pulse width of the reference clock, but the frequency of the master clock is one half the frequency of the reference clock. Likewise, a slave clock signal is formed which has a high pulse width T10a which is approximately the same as the high pulse width of the reference clock, but the frequency of the slave clock is also one half the frequency of the reference clock. The high pulse width of either or both the master clock signal and slave clock signal is then widened by an analog delay means, but by an amount T13 and T14 which is less than the low pulse width of the reference clock, so that the master clock signal and the slave clock signal do not overlap each other. As the propagation time of circuit elements within the integrated circuit varies due to changes in operating temperature or voltage, the analog delay T13 and T14 is changed proportionally to compensate for the changes in propagation time of the circuit elements.
    • 提供了一种用于形成用于集成电路的非重叠时钟信号402和404的方法。 使用其频率是集成电路的期望工作频率的两倍的参考时钟300。 形成具有与参考时钟的高脉冲宽度大致相同的高脉冲宽度T9a的主时钟信号，但是主时钟的频率是参考时钟的频率的一半。 类似地，形成具有与参考时钟的高脉冲宽度大致相同的高脉冲宽度T10a的从时钟信号，但从时钟的频率也是参考时钟的频率的一半。 主时钟信号和从时钟信号中的一个或两个的高脉冲宽度然后被模拟延迟装置加宽，但是小于参考时钟的低脉冲宽度的量T13和T14，使得主时钟 信号和从时钟信号不重叠。 由于集成电路中的电路元件的传播时间由于工作温度或电压的变化而变化，所以模拟延迟T13和T14按比例变化以补偿电路元件的传播时间的变化。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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