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81. 发明授权

US6157234A Pulse signal output circuit 有权
标题翻译：脉冲信号输出电路
公开(公告)号：US6157234A
公开(公告)日：2000-12-05
申请号：US233103
申请日：1999-01-19
申请人： Hiroshi Yamaguchi
发明人： Hiroshi Yamaguchi
IPC分类号： H03K5/04 , H03K5/13 , H03K5/131 , H03K5/151 , H03K5/156 , H03H11/26
CPC分类号： H03K5/1565
摘要： An integrated circuit has a first circuit which receives an input signal and outputs a first output signal, wherein the first output signal is produced by changing the pulse width of the input signal, a second circuit which receives the first output signal and outputs a second output signal, wherein the second output signal is produced by delaying the first output signal and a control circuit. The control circuit has a first control circuit which receives the first and second output signals and controls the first circuit based on the first and second output signals and a second control circuit which receives the first and second output signals and controls the second based on the first and second output signals.
摘要翻译：集成电路具有接收输入信号并输出第一输出信号的第一电路，其中通过改变输入信号的脉冲宽度来产生第一输出信号;第二电路，接收第一输出信号并输出第二输出信号，其中通过延迟所述第一输出信号和控制电路来产生所述第二输出信号。控制电路具有第一控制电路，其接收第一和第二输出信号并且基于第一和第二输出信号控制第一电路;以及第二控制电路，其接收第一和第二输出信号并基于第一输出信号控制第二输出信号和第二输出信号。

82. 发明授权

US6111794A Memory interface circuit including bypass data forwarding with essentially no delay 有权
标题翻译：存储器接口电路包括基本上没有延迟的旁路数据转发
公开(公告)号：US6111794A
公开(公告)日：2000-08-29
申请号：US342020
申请日：1999-06-28
申请人： John Christian Holst
发明人： John Christian Holst
IPC分类号： G06F7/02 , G06F12/10 , G11C5/14 , G11C7/06 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/14 , G11C11/408 , G11C11/412 , G11C11/418 , G11C29/00 , G11C29/02 , G11C29/18 , G11C29/32 , G11C29/44 , G11C29/50 , H03K3/356 , H03K5/00 , H03K5/13 , H03K5/151 , H03L7/08 , H03L7/099
CPC分类号： G11C29/84 , G06F12/1054 , G06F7/02 , G11C11/4087 , G11C11/412 , G11C11/418 , G11C29/02 , G11C29/021 , G11C29/025 , G11C29/026 , G11C29/028 , G11C29/18 , G11C29/32 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C5/147 , G11C7/06 , G11C7/062 , G11C7/065 , G11C7/1006 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/14 , H03K3/356113 , H03K3/356156 , H03K5/13 , H03K5/151 , H03L7/08 , G11C11/401 , G11C11/41 , G11C16/04 , G11C17/14 , G11C2029/5004 , G11C2029/5006 , G11C29/44 , H03K2005/00019 , H03K2005/00071 , H03L7/0995
摘要： A circuit and operating technique acquires input write data available at the beginning of the first half cycle and passes the write data to read terminals, bypassing read data from a memory cell that is read during the first half cycle, while incurring no read access penalty. The circuit and operating technique bypass the input write data to the read terminal in place of data transferred from the memory cells. The data is forwarded to an node having a relatively large capacitance by connecting to the node very small devices with a small capacitance and with the small devices operating in saturation. The relatively large capacitance of the node is exploited to achieve a multiplexing functionality with effectively no delay.
摘要翻译：电路和操作技术获取在前半周期开始时可用的输入写入数据，并将写入数据传送到读取终端，绕过来自在前半个周期期间读取的存储器单元的读取数据，同时不产生读取访问损失。电路和操作技术将输入写入数据旁路到读取终端，代替从存储器单元传送的数据。通过连接到节点具有小电容的小型器件并且小器件工作在饱和状态，将数据转发到具有相对较大电容的节点。节点的相对较大的电容被利用来实现无效延迟的复用功能。

83. 发明授权

US6104225A Semiconductor device using complementary clock and signal input state detection circuit used for the same 失效
标题翻译：半导体器件采用互补时钟和信号输入状态检测电路相同
公开(公告)号：US6104225A
公开(公告)日：2000-08-15
申请号：US76810
申请日：1998-05-13
申请人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
发明人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
IPC分类号： G11C7/22 , H03K5/00 , H03K5/135 , H03K5/151 , H03L7/081 , G06F1/04
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/135 , H03K5/151 , H03K2005/00234 , H03L7/0814
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180.degree. phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A 1/2 phase clock generating circuit generates a 1/2 phase shift signal 180.degree. out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the 1/2 phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.
摘要翻译：公开了一种半导体器件，用于从外部时钟产生彼此互补的第一和第二内部时钟，并且可用于使用互补时钟的系统和内部产生180°相位时钟的系统的系统。第一时钟输入电路（缓冲器）被提供有第一外部时钟并输出第一内部时钟。第二时钟输入电路（缓冲器）被提供有与第一外部时钟互补的第二外部时钟并输出第二时钟。 A + E，fra 1/2 + EE相位时钟发生电路产生与第一内部时钟异相180°的+ E，fra 1/2 + EE相移信号。第二外部时钟状态检测电路判断第二外部时钟是否被输入到第二时钟输入缓冲器。当第二外部时钟被输入时，开关被操作以产生第二时钟作为第二内部时钟，并且当第二外部时钟未被输入时产生+ E，fra 1/2 + EE相移信号作为第二内部时钟，根据第二外部时钟状态检测电路的判断。

84. 发明授权

US6094079A Sequencer module for a pulse width modulation driver 失效
标题翻译：用于脉冲宽度调制驱动器的音序器模块
公开(公告)号：US6094079A
公开(公告)日：2000-07-25
申请号：US216902
申请日：1998-12-21
申请人： Brian L. Boggs , Paul C. Gottshall , Steven O. Hart , Brian G. McGee
发明人： Brian L. Boggs , Paul C. Gottshall , Steven O. Hart , Brian G. McGee
IPC分类号： H03K5/151 , H03K7/08 , H03K3/017
CPC分类号： H03K5/1515 , H03K7/08
摘要： A driver for producing a desired pulse width modulated current through a load is provided with a sequencer for generating a plurality of wave forms phase-shifted so as to have non-overlapping duty cycles. A target generator supplies a target current value to a comparator, which compares the target current value to a signal representative of a sensed current flowing through the load. A driver control is responsive to a duty-cycle of only one of the plurality of wave forms to selectively generate trigger signals for switching current through the load in response to the result of the comparison.
摘要翻译：用于通过负载产生期望的脉冲宽度调制电流的驱动器设置有用于产生相移的多个波形以便具有非重叠占空比的定序器。目标发生器将目标电流值提供给比较器，比较器将目标电流值与表示流过负载的感测电流的信号进行比较。驱动器控制响应于多个波形中的仅一个的占空比响应于比较的结果来选择性地产生用于切换通过负载的电流的触发信号。

85. 发明授权

US6046621A Differential signal generator with dynamic beta ratios 失效
标题翻译：具有动态β比率的差分信号发生器
公开(公告)号：US6046621A
公开(公告)日：2000-04-04
申请号：US938193
申请日：1997-09-26
申请人： Matthew P. Crowley
发明人： Matthew P. Crowley
IPC分类号： G11C7/06 , G11C7/10 , G11C7/22 , G11C8/14 , G11C11/418 , G11C29/02 , G11C29/32 , G11C29/50 , H03K5/00 , H03K5/13 , H03K5/151 , H03L7/08 , H03L7/099 , H03L5/00
CPC分类号： G11C29/026 , G11C11/418 , G11C29/02 , G11C29/021 , G11C29/025 , G11C29/028 , G11C29/32 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C7/065 , G11C7/1006 , G11C7/22 , G11C8/14 , H03K5/13 , H03K5/151 , H03L7/08 , G11C11/401 , G11C11/41 , G11C16/04 , G11C17/14 , G11C2029/5004 , G11C2029/5006 , H03K2005/00019 , H03K2005/00071 , H03L7/0995
摘要： A differential signal generator for generating a true/complement output signal pair in response to a single-ended input signal is disclosed. The differential signal generator includes an input stage that generates a true/complement intermediate signal pair in response to the input signal, and first and second inverters that generate the output signal pair in response to the intermediate signal pair. The first and second inverters have dynamic beta ratios that change in response to the input signal. This is accomplished by coupling a transistor in the first inverter to ground and decoupling a transistor in the second inverter from ground when the input signal has a high value, and decoupling the transistor in the first inverter from ground and coupling the transistor in the second inverter to ground when the input signal has a low value. As a result, the output signal pair cross each other at a predetermined cross-point although the intermediate signal pair does not.
摘要翻译：公开了一种用于响应于单端输入信号产生真/补输出信号对的差分信号发生器。差分信号发生器包括响应于输入信号产生真/补中间信号对的输入级，以及响应于中间信号对产生输出信号对的第一和第二反相器。第一和第二逆变器具有响应于输入信号而变化的动态β比率。这是通过将第一反相器中的晶体管耦合到地，并且当输入信号具有高值时将第二反相器中的晶体管与地耦合并且将第一反相器中的晶体管与地耦合并且将第二反相器中的晶体管耦合当输入信号具有低值时接地。结果，虽然中间信号对没有，输出信号对在预定的交叉点彼此交叉。

86. 发明授权

US5952863A Circuit and method for generating non-overlapping clock signals for an integrated circuit 失效
标题翻译：用于为集成电路产生非重叠时钟信号的电路和方法
公开(公告)号：US5952863A
公开(公告)日：1999-09-14
申请号：US762169
申请日：1996-12-09
申请人： Jason A.T. Jones , Gary L. Swoboda
发明人： Jason A.T. Jones , Gary L. Swoboda
IPC分类号： G06F1/06 , H03K5/151 , H03K5/19 , H03K5/15
CPC分类号： H03K5/1515
摘要： A method is provided for forming non-overlapping clock signals 402 and 404 for an integrated circuit. A reference clock 300 whose frequency is twice that of a desired operating frequency for the integrated circuit is used. A master clock signal is formed which has a high pulse width T9a which is approximately the same as the high pulse width of the reference clock, but the frequency of the master clock is one half the frequency of the reference clock. Likewise, a slave clock signal is formed which has a high pulse width T10a which is approximately the same as the high pulse width of the reference clock, but the frequency of the slave clock is also one half the frequency of the reference clock. The high pulse width of either or both the master clock signal and slave clock signal is then widened by an analog delay means, but by an amount T13 and T14 which is less than the low pulse width of the reference clock, so that the master clock signal and the slave clock signal do not overlap each other. As the propagation time of circuit elements within the integrated circuit varies due to changes in operating temperature or voltage, the analog delay T13 and T14 is changed proportionally to compensate for the changes in propagation time of the circuit elements.
摘要翻译：提供了一种用于形成用于集成电路的非重叠时钟信号402和404的方法。使用其频率是集成电路的期望工作频率的两倍的参考时钟300。形成具有与参考时钟的高脉冲宽度大致相同的高脉冲宽度T9a的主时钟信号，但是主时钟的频率是参考时钟的频率的一半。类似地，形成具有与参考时钟的高脉冲宽度大致相同的高脉冲宽度T10a的从时钟信号，但从时钟的频率也是参考时钟的频率的一半。主时钟信号和从时钟信号中的一个或两个的高脉冲宽度然后被模拟延迟装置加宽，但是小于参考时钟的低脉冲宽度的量T13和T14，使得主时钟信号和从时钟信号不重叠。由于集成电路中的电路元件的传播时间由于工作温度或电压的变化而变化，所以模拟延迟T13和T14按比例变化以补偿电路元件的传播时间的变化。

87. 发明授权

US5945863A Analog delay circuit 失效
标题翻译：模拟延迟电路
公开(公告)号：US5945863A
公开(公告)日：1999-08-31
申请号：US878162
申请日：1997-06-18
申请人： Bruce H. Coy
发明人： Bruce H. Coy
IPC分类号： H03K5/151 , H03L7/099 , H03K5/13 , H03K17/28
CPC分类号： H03K5/151 , H03L7/0995
摘要： An analog delay circuit provide a current-dependent delay through two differential pairs of transistors operated in parallel, one with input resistors, the other without. Delay is varied through the delay stage by provision of complementary currents produced by a current DAC in response to digital code provided in a data bus. The complementary currents drive the differential pairs to various combinations of operations, which yields the desired variable delay.
摘要翻译：模拟延迟电路通过并联运行的两个差分对晶体管提供依赖于电流的延迟，一个具有输入电阻，另一个不带。响应于在数据总线中提供的数字代码，通过提供由当前DAC产生的互补电流，延迟在延迟阶段变化。互补电流将差分对驱动到各种操作组合，这产生期望的可变延迟。

88. 发明授权

US5912569A Methods, circuits and devices for improving crossover performance and/or monotonicity, and applications of the same in a universal serial bus (USB) low speed output driver 失效
标题翻译：用于提高交叉性能和/或单调性的方法，电路和设备及其在通用串行总线（USB）低速输出驱动器中的应用
公开(公告)号：US5912569A
公开(公告)日：1999-06-15
申请号：US934933
申请日：1997-09-22
申请人： Gary W. Alleven
发明人： Gary W. Alleven
IPC分类号： H03K5/151 , H03K19/00 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/00323 , H03K19/0013 , H03K19/00361 , H03K19/00384 , H03K5/151
摘要： A circuit comprising a first driver circuit, a second driver circuit and a delay circuit. The first driver circuit may be configured to generate a first output signal and a control signal in response to a first input signal. The delay circuit may be configured to generate a delay signal in response to a second input signal and the control signal. The second driver circuit may be configured to generate a second output signal in response to the delay signal.
摘要翻译：一种包括第一驱动电路，第二驱动电路和延迟电路的电路。第一驱动器电路可以被配置为响应于第一输入信号产生第一输出信号和控制信号。延迟电路可以被配置为响应于第二输入信号和控制信号而产生延迟信号。第二驱动器电路可以被配置为响应于延迟信号而产生第二输出信号。

89. 发明授权

US5867453A Self-setup non-overlap clock generator 失效
标题翻译：自设置非重叠时钟发生器
公开(公告)号：US5867453A
公开(公告)日：1999-02-02
申请号：US019686
申请日：1998-02-06
申请人： Shyh-Jye Wang , Chi-Chiang Wu , Hsing-Chien Huang
发明人： Shyh-Jye Wang , Chi-Chiang Wu , Hsing-Chien Huang
IPC分类号： H03K5/151 , G04F8/00 , H03K3/037 , H03K5/13
CPC分类号： H03K5/1515
摘要： A self-setup non-overlap clock generator is disclosed. This clock generator includes a primary clock signal input terminal for providing a primary clock signal, and a selection signal input terminal for providing at least one selection signal. The present invention also includes a first logic gate having a first input terminal coupled to receive an inverted signal of the primary clock signal. Further, a second logic gate is provided, having a first input terminal coupled to receive the primary clock signal. A first programmable delay portion is used to delay an output signal from the first logic gate an amount of time according to the selection signal, and a second programmable delay portion is used to delay an output signal from the second logic gate a predetermined amount of time according to the selection signal. Therefore, a first clock signal is generated from the output of the first logic gate, and a second clock signal is generated from the output of the second logic gate. Particularly, the present invention includes a test circuit to determine whether a non-overlap space between the first clock signal and the second clock signal conforms to a predetermined value. Finally, a selector is used to generate the at least one selection signal in response to at least one output of the test circuit such that a smallest value out of all possible non-overlap spaces is chosen.
摘要翻译：公开了一种自建非重叠时钟发生器。该时钟发生器包括用于提供主时钟信号的主时钟信号输入端和用于提供至少一个选择信号的选择信号输入端。本发明还包括具有耦合以接收主时钟信号的反相信号的第一输入端的第一逻辑门。此外，提供了第二逻辑门，其具有耦合以接收主时钟信号的第一输入端。第一可编程延迟部分用于根据选择信号将来自第一逻辑门的输出信号的时间量延迟，并且第二可编程延迟部分用于将来自第二逻辑门的输出信号延迟预定的时间量根据选择信号。因此，从第一逻辑门的输出产生第一时钟信号，并且从第二逻辑门的输出产生第二时钟信号。特别地，本发明包括测试电路，用于确定第一时钟信号和第二时钟信号之间的非重叠空间是否符合预定值。最后，选择器用于响应于测试电路的至少一个输出而产生至少一个选择信号，使得选择所有可能的非重叠空间中的最小值。

90. 发明授权

US5852378A Low-skew differential signal converter 失效
公开(公告)号：US5852378A
公开(公告)日：1998-12-22
申请号：US798228
申请日：1997-02-11
申请人： Brent Keeth
发明人： Brent Keeth
IPC分类号： H03K5/151 , H03K3/017
CPC分类号： H03K5/151
摘要： A low-skew single-ended to differential signal converter includes a conventional single-ended to differential converter that drives a pair of output driver circuits. Each driver circuit is formed from a pair of transfer gates that receive a supply voltage or a reference voltage, respectively. The transfer gates transfer only a portion of the supply or reference voltage in response to the inverted signal from the conventional converter. The portion of the transferred voltage is insufficient to trigger output members in the output drivers and the output voltages from the drivers do not transition in response to the noninverted signal. The inverted signal causes the outputs of the transfer gates to transition fully, triggering the respective output inverters. Because the inverted signal causes transitions of both of the output signals, skew of the output signals is reduced relative to skew of the inverted and noninverted signals.

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