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81. 发明授权

US06456520B1 Semiconductor memory and method for driving the same 失效
标题翻译：半导体存储器及其驱动方法
公开(公告)号：US06456520B1
公开(公告)日：2002-09-24
申请号：US09941736
申请日：2001-08-30
申请人： Yoshihisa Kato , Yasuhiro Shimada
发明人： Yoshihisa Kato , Yasuhiro Shimada
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： The semiconductor memory of this invention includes a plurality of ferroelectric capacitors successively connected to one another in a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof; a plurality of selecting transistors respectively connected to the plurality of ferroelectric capacitor in parallel for selecting a selected ferroelectric capacitor from the plural ferroelectric capacitors; a set line connected to a first end of a series circuit including the plural successively connected ferroelectric capacitors to which a reading voltage is applied; and a load capacitor connected to a second end of the series circuit for detecting displacement of polarization of the ferroelectric film of the selected ferroelectric capacitor. In the series circuit, capacitance is larger in a ferroelectric capacitor disposed in a position relatively near to the first end of the series circuit than in a ferroelectric capacitor disposed in a position relatively far from the first end.
摘要翻译：本发明的半导体存储器包括在位线方向上相继连接的多个铁电电容器，用于根据其铁电体膜的极化位移来存储数据; 分别与所述多个铁电电容器并联连接的多个选择晶体管，用于从所述多个铁电电容器中选择所选择的铁电电容器; 连接到串联电路的第一端的设定线，该串联电路包括多个依次连接的强电介质电容器，其中施加了读取电压; 连接到串联电路的第二端的负载电容器，用于检测所选铁电电容器的铁电体膜的极化位移。在串联电路中，布置在比串联电路的第一端更靠近串联电路的第一端的铁电电容器中的电容大于布置在距第一端相对较远的位置的铁电电容器中的电容。

82. 发明授权

US06452830B2 Memory configuration including a plurality of resistive ferroelectric memory cells 失效
标题翻译：存储器配置包括多个电阻型铁电存储单元
公开(公告)号：US06452830B2
公开(公告)日：2002-09-17
申请号：US09767805
申请日：2001-01-22
申请人： Oskar Kowarik , Kurt Hoffmann
发明人： Oskar Kowarik , Kurt Hoffmann
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A memory configuration includes a plurality of resistive ferroelectric memory cells. Each of the memory cells includes a selection transistor and a storage capacitor. The selection transistor has a given zone of a first conductivity type. The storage capacitor has a first and a second electrode. The first electrode is supplied with a fixed cell plate voltage, the second electrode is connected to the given zone of the first conductivity type. A source and a drain of a MOS transistor are supplied with the fixed cell plate voltage. The channel of the MOS transistor has a channel length extending over at least two of the memory cells. The given zone of the first conductivity type is connected, via a resistor, to the channel of the MOS transistor such that the given zone is electrically connected to the first electrode of the storage capacitor via the resistor and the MOS transistor.
摘要翻译：存储器配置包括多个电阻式铁电存储单元。每个存储单元包括选择晶体管和存储电容器。选择晶体管具有第一导电类型的给定区域。存储电容器具有第一和第二电极。第一电极被提供有固定电池板电压，第二电极连接到第一导电类型的给定区域。 MOS晶体管的源极和漏极被提供有固定电池板电压。 MOS晶体管的沟道具有在至少两个存储单元上延伸的沟道长度。第一导电类型的给定区域经由电阻器连接到MOS晶体管的沟道，使得给定区域经由电阻器和MOS晶体管电连接到存储电容器的第一电极。

83. 发明授权

US06445608B1 Ferroelectric random access memory configurable output driver circuit 有权
标题翻译：铁电随机存取存储器可配置输出驱动电路
公开(公告)号：US06445608B1
公开(公告)日：2002-09-03
申请号：US09950560
申请日：2001-09-10
申请人： Kurt Schwartz , Michael Alwais
发明人： Kurt Schwartz , Michael Alwais
IPC分类号： G11C1122
CPC分类号： G11C7/1051 , G11C11/22
摘要： A FRAM configurable output driver circuit allows the user to configure the output driver for either CMOS level push/pull operation or true open drain operation. This configuration is stored in a non-volatile memory including a FRAM cell and a standard logic latch. The configuration data is restored to the latch on powerup. The user is able to change the configuration at any time. Any changes to the configuration are stored in the non-volatile memory.
摘要翻译： FRAM可配置输出驱动器电路允许用户配置输出驱动器，用于CMOS电平推/拉操作或真开漏工作。该配置存储在包括FRAM单元和标准逻辑锁存器的非易失性存储器中。配置数据在上电时恢复到锁存器。用户可以随时更改配置。配置的任何更改都存储在非易失性存储器中。

84. 发明授权

US06438020B1 Ferroelectric memory device having an internal supply voltage, which is lower than the external supply voltage, supplied to the memory cells 有权
标题翻译：提供给存储单元的具有低于外部电源电压的内部电源电压的铁电存储器件
公开(公告)号：US06438020B1
公开(公告)日：2002-08-20
申请号：US09651104
申请日：2000-08-30
申请人： Junichi Yamada
发明人： Junichi Yamada
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： There is provided a highly reliable non-volatile ferroelectric memory device in which the permitted number of read/write operation cycles is increased. The device comprises a step-down power supply circuit which generates a supply voltage VINT which is lower than a supply voltage VDD fed from the outside but not less than a coercive voltage of the ferroelectrics for the purpose of improving the resistance to fatigue of and imprinting to the ferroelectrics. Since the characteristics of the ferroelectrics deteriorate more due to fatigue and imprinting as the voltage applied to the ferroelectrics increases, a supply voltage for sense amplifiers and voltage supply circuits are selected to be VINT so that VINT is applied to the ferroelectric capacitors, while a supply voltage for other peripheral circuits is selected to be VDD. With this structure, the reliability of the device with respect to its read/write operations can significantly be improved as compared to the conventional ferroelectric memory devices by minimizing the effect that the signal voltage is reduced and by increasing the permitted number of operation cycles.
摘要翻译：提供了一种高度可靠的非易失性铁电存储器件，其中允许的读/写操作次数增加。该装置包括降压电源电路，其生成低于从外部馈送的电源电压VDD但不低于铁电体的矫顽电压的电源电压VINT，以提高耐疲劳性和印记性到铁电体。由于随着施加到铁电体上的电压的增加，铁电体的特性由于疲劳和压印而变差，因此将读出放大器和电压供给电路的电源电压选择为VINT，以将VINT施加到铁电电容器，同时供给其他外围电路的电压选择为VDD。利用这种结构，与传统的铁电存储器件相比，器件相对于其读/写操作的可靠性可以通过最小化信号电压降低的影响和通过增加允许的操作周期数而显着提高。

85. 发明授权

US06434039B1 Circuit configuration for reading a memory cell having a ferroelectric capacitor 有权
标题翻译：用于读取具有铁电电容器的存储单元的电路配置
公开(公告)号：US06434039B1
公开(公告)日：2002-08-13
申请号：US09838750
申请日：2001-04-19
申请人： Georg Braun , Heinz Hönigschmid
发明人： Georg Braun , Heinz Hönigschmid
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A circuit configuration for reading a ferroelectric memory cell which has a ferroelectric capacitor is described. The memory cell is connected to a bit line. The circuit configuration provides a differential amplifier having a first differential amplifier input, a second differential amplifier input and a differential amplifier output. The first differential amplifier input is connected to the bit line, and the second differential amplifier input is connected to a reference signal. A first driver input of a first driver circuit is connected to the differential amplifier output, and a first driver output is connected to the bit line. The differential amplifier is fed back through the first driver circuit and regulates the bit line voltage to the voltage value of the reference signal.
摘要翻译：描述用于读取具有铁电电容器的铁电存储单元的电路结构。存储单元连接到位线。电路配置提供了具有第一差分放大器输入，第二差分放大器输入和差分放大器输出的差分放大器。第一差分放大器输入连接到位线，第二差分放大器输入连接到参考信号。第一驱动电路的第一驱动器输入端连接到差分放大器输出，第一驱动器输出端连接到位线。差分放大器通过第一驱动电路反馈，并将位线电压调节到参考信号的电压值。

86. 发明授权

US06434038B1 Non-volatile memory using ferroelectric material and manufacturing method thereof 有权
标题翻译：使用铁电材料的非易失性存储器及其制造方法
公开(公告)号：US06434038B1
公开(公告)日：2002-08-13
申请号：US09791760
申请日：2001-02-26
申请人： Morihumi Ohno
发明人： Morihumi Ohno
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A non-volatile memory including a storage device composed of a ferroelectric material having first and second remaining polarization characteristics offset from each other. Selection of a first or a second remaining polarization characteristic is determined by a predetermined voltage applied to the ferroelectric material. A controller outputs a control signal, in response to a predetermined address signal, which is applied to the storage device and the controller. The address signal includes for each address a data portion and an offset portion, the offset portion corresponding to either the first or the second remaining polarization characteristic. The control signal couples a first predetermined voltage to the storage device when the offset portion of the address signal corresponds to the first remaining polarization characteristic and couples a second predetermined voltage to the storage device when the offset portion of the address signal corresponds to the second remaining polarization characteristic. A reader coupled to the controller outputs data from the storage device at a remaining polarization value selected by the address signal in accordance with the control signal.
摘要翻译：一种非易失性存储器，包括由具有彼此偏移的第一和第二剩余极化特性的铁电材料构成的存储装置。选择第一或第二剩余极化特性由施加到铁电材料的预定电压来确定。控制器响应于预定的地址信号输出一个控制信号，该地址信号被施加到存储设备和控制器。地址信号为每个地址包括数据部分和偏移部分，偏移部分对应于第一或第二剩余极化特性。当地址信号的偏移部分对应于第一剩余极化特性时，控制信号将第一预定电压耦合到存储装置，并且当地址信号的偏移部分对应于第二剩余极化特性时将第二预定电压耦合到存储装置极化特性。耦合到控制器的读取器根据控制信号以由地址信号选择的剩余极化值从存储装置输出数据。

87. 发明授权

US06388915B1 Method for driving semiconductor memory 有权
标题翻译：驱动半导体存储器的方法
公开(公告)号：US06388915B1
公开(公告)日：2002-05-14
申请号：US09941650
申请日：2001-08-30
申请人： Yoshihisa Kato , Yasuhiro Shimada
发明人： Yoshihisa Kato , Yasuhiro Shimada
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A cell selecting transistor serially connected to a data read ferroelectric capacitor selected from plural ferroelectric capacitors for data read is turned on and other cell selecting transistors serially connected to the other ferroelectric capacitors are turned off. Thus, one electrode of the data read ferroelectric capacitor is connected to a set line through a first common node, and the other electrode of the data read ferroelectric capacitor is connected to a load capacitor through a second common node. Next, after a reading voltage is applied to the set line so as to read a data stored in the data read ferroelectric capacitor, the reading voltage applied to the set line is removed. The reading voltage is set to such magnitude that displacement of polarization of the ferroelectric film of the data read ferroelectric capacitor is restored to that obtained before reading a data by removing the reading voltage.
摘要翻译：串联连接到从用于数据读取的多个铁电电容器中选择的数据读取铁电体电容器的单元选择晶体管导通，并且与另一个强电介质电容器串联连接的其他单元选择晶体管截止。因此，数据读取铁电电容器的一个电极通过第一公共节点连接到设定线，并且数据读取铁电电容器的另一个电极通过第二公共节点连接到负载电容器。接下来，在将读取电压施加到设定线以便读取存储在数据读取铁电电容器中的数据之后，去除施加到设定线的读取电压。读取电压被设定为使数据读取铁电体电容器的铁电体膜的极化位移恢复到通过去除读取电压而读取数据之前获得的极化电位。

88. 发明授权

US06373744B1 Ferroelectric memory 有权
标题翻译：铁电存储器
公开(公告)号：US06373744B1
公开(公告)日：2002-04-16
申请号：US09911831
申请日：2001-07-25
申请人： Yoshitaka Mano
发明人： Yoshitaka Mano
IPC分类号： G11C1122
CPC分类号： G11C29/50 , G11C11/22
摘要： To provide a ferroelectric memory, in which data can be positively protected even in an event of fluctuations in process parameter, time can be shortened for a reliability estimation test, and it is possible to avoid device breakage resulted from the test. A source voltage VDD is detected by using a source voltage detection circuit having a stable detection level. When a detected voltage RREFA is at or lower than a set detection level VREFA, an external input terminal XEXTCE is deactivated by using an output signal of a differential amplifier circuit to protect data. Thus, it is possible to protect data with stability.
摘要翻译：为了提供铁电存储器，即使在工艺参数波动的情况下也可以正确地保护数据，因此可靠性估计测试的时间可以缩短，并且可以避免由于测试而导致的器件损坏。通过使用具有稳定检测电平的源极电压检测电路来检测源极电压VDD。当检测电压RREFA处于或低于设定的检测电平VREFA时，通过使用差分放大器电路的输出信号来去除外部输入端子XEXTCE以保护数据。因此，可以稳定地保护数据。

89. 发明授权

US06370056B1 Ferroelectric memory and method of operating same 失效
标题翻译：铁电存储器和操作方法相同
公开(公告)号：US06370056B1
公开(公告)日：2002-04-09
申请号：US09523492
申请日：2000-03-10
申请人： Zheng Chen , Vikram Joshi , Myoungho Lim , Carlos A. Paz de Araujo , Larry D. McMillan
发明人： Zheng Chen , Vikram Joshi , Myoungho Lim , Carlos A. Paz de Araujo , Larry D. McMillan
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric non-volatile memory comprising: a plurality of memory cells, each containing an FeFET and a MOSFET, each of said FeFETs having a source, a drain, a substrate, and a gate, and each MOSFET having a pair of source/drains and a gate. The cells are arranged in an array comprising a plurality of rows and a plurality of columns. A gate line and a bit line are associated with each column, and a word line, a drain line, and a substrate line are associated with each row. One source/drain of each MOSFET is connected to its corresponding gate line; the other source/drain is connected to the gate of the FeFET in the cell. The gate of the MOSFET is connected to its corresponding word line which provides a write and erase enable signal. The drain of the FeFET is connected to its corresponding drain line, and the source of the FeFET is connected to its corresponding bit line. The substrate of each FeFET is connected to its corresponding substrate line. A read MOSFET is connected between a drain input and the drain line associated with each row. The gate of the read MOSFET is connected to an input for the read enable signal.
摘要翻译：一种铁电非易失性存储器，包括：多个存储单元，每个存储单元包含FeFET和MOSFET，每个所述FeFET具有源极，漏极，衬底和栅极，并且每个MOSFET具有一对源极/漏极和一个门。单元被布置成包括多行和多列的阵列。栅极线和位线与每列相关联，并且字线，漏极线和衬底线与每一行相关联。每个MOSFET的一个源极/漏极连接到其对应的栅极线; 另一个源极/漏极连接到电池中的FeFET的栅极。 MOSFET的栅极连接到提供写和擦除使能信号的相应字线。 FeFET的漏极连接到其对应的漏极线，并且FeFET的源极连接到其对应的位线。每个FeFET的衬底连接到其相应的衬底线。读取MOSFET连接在与每行相关联的漏极输入和漏极线之间。读取MOSFET的栅极连接到读使能信号的输入端。

90. 发明授权

US06366489B1 Bi-state ferroelectric memory devices, uses and operation 失效
标题翻译：双态铁电存储器件，用途和操作
公开(公告)号：US06366489B1
公开(公告)日：2002-04-02
申请号：US09652392
申请日：2000-08-31
申请人： Craig T. Salling
发明人： Craig T. Salling
IPC分类号： G11C1122
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11507
摘要： Bi-state ferroelectric-MOS (FMOS) capacitors are adapted for use in memory cells of a memory device. Bi-state ferroelectric memory cells have a bottom plate of a capacitor coupled to a first source/drain region of a pass transistor, a gate of the pass transistor coupled to a word line, and a second source/drain region of the pass transistor coupled to a bit line. A plate line is coupled to the top plate of the capacitor to facilitate programming of the polarization state of a ferroelectric portion of the capacitor. The polarization state of the ferroelectric portion of the capacitor causes a depletion or accumulation of electrons in the bottom plate of the capacitor, thus altering its capacitance value. The resulting capacitance value may be sensed without causing a polarization reversal of the ferroelectric portion of the capacitor. Accordingly, bi-state ferroelectric memory cells of the various embodiments function as non-volatile memory cells.
摘要翻译：双态铁电MOS（FMOS）电容器适用于存储器件的存储单元。双态铁电存储器单元具有耦合到传输晶体管的第一源极/漏极区域的电容器的底板，耦合到字线的通过晶体管的栅极和耦合的通过晶体管的第二源极/漏极区域耦合到一点点板线耦合到电容器的顶板以便于编程电容器的铁电部分的偏振状态。电容器的铁电部分的极化状态引起电容器底板中的电子的耗尽或累积，从而改变其电容值。可以在不引起电容器的铁电部分的极化反转的情况下感测所得到的电容值。因此，各种实施例的双态铁电存储单元用作非易失性存储单元。

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