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81. 发明申请

US20180074955A1 TIME DE-INTERLEAVING CIRCUIT AND TIME DE-INTERLEAVING METHOD 审中-公开
公开(公告)号：US20180074955A1
公开(公告)日：2018-03-15
申请号：US15486394
申请日：2017-04-13
申请人： MStar Semiconductor, Inc.
发明人： CHUN-CHIEH WANG
IPC分类号： G06F12/06 , H04N21/232
CPC分类号： G06F12/0646 , G06F12/0607 , G06F2212/1024 , G06F2212/174 , H03M13/276 , H03M13/2764 , H03M13/2782 , H03M13/6552 , H04N21/2326 , H04N21/426 , H04N21/4382
摘要： A time de-interleaving circuit is located at a signal receiver of a communication system to perform a time de-interleaving process on an interleaved signal. The interleaved signal includes a plurality of information units, which include a plurality of data units and a plurality of common units. The time de-interleaving circuit includes: a data unit access address generator, generating a plurality of data unit access addresses according to a first address sequence to accordingly access the plurality of data units in a memory; and a common unit access address generator, generating a plurality of common unit access addresses according to a second address sequence to accordingly access the plurality of common units in the memory. The second address sequence is a reverse sequence of the first address sequence.

82. 发明申请

US20150301940A1 Self-Configurable Device for Interleaving/Deinterleaving Data Frames 有权
标题翻译：用于交织/解交织数据帧的自配置设备
公开(公告)号：US20150301940A1
公开(公告)日：2015-10-22
申请号：US14380554
申请日：2013-02-22
申请人： UNIVERSITE DE BRETAGNE SUD , CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE - CNRS
发明人： Philippe COUSSY , Cyrille CHAVET
IPC分类号： G06F12/06 , G06F13/28
CPC分类号： G06F12/0607 , G06F13/28 , G06F2212/251 , H03M13/1102 , H03M13/2764 , H03M13/2775 , H03M13/2789 , H03M13/6513 , H03M13/6519 , H03M13/6569
摘要： A device for interleaving/deinterleaving digital data delivered by processing elements (P0 . . . Pn-1) suitable for being used both with turbo-codes and with LDPC codes. The device includes memory banks (B0 . . . Bm-1) for storing data coming from or going to the processing elements, an interconnection network (INT) for directing the data between the processing elements and the memory banks, and a control unit (CTRL) for controlling the interconnection network and the memory banks. The control unit (CTRL) includes a calculation circuit (CAL) capable of the online generation of command words for the interconnection network and addressing and control sequences of the memory banks, ensuring conflict-free memory access on the basis of the interleaving rule to be applied, the size of the digital data frames, the number of processing units and memory banks, and the interconnection network.
摘要翻译：一种用于对适于与turbo码和LDPC码一起使用的处理单元（P0.Pn-1）传送的数字数据进行交织/解交织的装置。该设备包括用于存储来自或去往处理元件的数据的存储体（B0 ... Bm-1），用于在处理元件和存储体之间引导数据的互连网络（INT），以及控制单元 CTRL），用于控制互连网络和存储体。控制单元（CTRL）包括能够在线地产生互连网络的命令字和存储体的寻址和控制序列的计算电路（CAL），确保基于交织规则的无冲突存储器访问为应用，数字数据帧的大小，处理单元和存储体的数量以及互连网络。

83. 发明授权

US08773944B2 Concurrent multiple-dimension word-addressable memory architecture 有权
标题翻译：并行多维字符寻址存储器架构
公开(公告)号：US08773944B2
公开(公告)日：2014-07-08
申请号：US13368752
申请日：2012-02-08
申请人： Chihtung Chen , Inyup Kang , Viraphol Chaiyakul
发明人： Chihtung Chen , Inyup Kang , Viraphol Chaiyakul
IPC分类号： G11C7/10
CPC分类号： G11C8/10 , G06F12/0207 , G11C8/16 , H03M13/2707 , H03M13/2764
摘要： An N-dimension addressable memory is disclosed. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.
摘要翻译：公开了一种N维可寻址存储器。存储器包括位元组的N维阵列和配置为使用N维度寻址（NDA）来寻址每个位单元的逻辑，其中N至少为2，并且位单元阵列可由N个正交地址空间寻址。 N维可寻址存储器的每个位单元包括位存储元件，N个字线和N个位线。

84. 发明授权

US08621322B2 Data interleaver 有权
标题翻译：数据交织器
公开(公告)号：US08621322B2
公开(公告)日：2013-12-31
申请号：US12286359
申请日：2008-09-30
申请人： Mohit K. Prasad , Clark H. Jarvis
发明人： Mohit K. Prasad , Clark H. Jarvis
IPC分类号： H03M13/27 , H03M13/53
CPC分类号： H03M13/2771 , H03M13/271 , H03M13/2714 , H03M13/2764 , H03M13/2957 , H04L1/0066 , H04L1/0071
摘要： Methods and corresponding systems in an interleaver include loading K symbol data, in a linear order, into a matrix memory having (R·C) storage locations corresponding R rows and C columns. A sequence of interleaved addresses is produced for reading the K symbol data in an interleaved order from the matrix memory. Next, (R·C)−K interleaved addresses are queued in a first-in-first-out (FIFO) memory. After queuing (R·C)−K interleaved addresses in the FIFO memory, symbol data is output using the interleaved addresses in the FIFO memory to address and output the symbol data in the matrix memory in the interleaved order. The FIFO memory can contain at least 234 memory locations.
摘要翻译：交织器中的方法和对应系统包括将K个符号数据以线性顺序加载到具有对应于R行和C列的（R·C）存储位置的矩阵存储器中。产生用于从矩阵存储器以交错顺序读取K个符号数据的交织地址序列。接下来，（R·C）-K交织地址在先进先出（FIFO）存储器中排队。在FIFO存储器中排队（R·C）-K交错地址之后，使用FIFO存储器中的交错地址输出符号数据，以交错顺序对矩阵存储器中的符号数据进行寻址和输出。 FIFO存储器可以包含至少234个存储单元。

85. 发明申请

US20120134229A1 CONCURRENT MULTIPLE-DIMENSION WORD-ADDRESSABLE MEMORY ARCHITECTURE 有权
标题翻译：同时存在多个字节的可寻址存储器架构
公开(公告)号：US20120134229A1
公开(公告)日：2012-05-31
申请号：US13368752
申请日：2012-02-08
申请人： Chihtung Chen , Inyup Kang , Viraphol Chaiyakul
发明人： Chihtung Chen , Inyup Kang , Viraphol Chaiyakul
IPC分类号： G11C8/06
CPC分类号： G11C8/10 , G06F12/0207 , G11C8/16 , H03M13/2707 , H03M13/2764
摘要： An N-dimension addressable memory is disclosed. The memory includes an N-dimension array of bit ceils and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.
摘要翻译：公开了一种N维可寻址存储器。存储器包括位细胞的N维阵列和被配置为使用N维度寻址（NDA）寻址每个位单元的逻辑，其中N至少为2，并且位单元阵列可由N个正交地址空间寻址。 N维可寻址存储器的每个位单元包括位存储元件，N个字线和N个位线。

86. 发明申请

US20120047414A1 ADDRESS GENERATION APPARATUS AND METHOD FOR QUADRATIC PERMUTATION POLYNOMIAL INTERLEAVER 有权
标题翻译：地址生成装置和方法用于四元制多边形交织器
公开(公告)号：US20120047414A1
公开(公告)日：2012-02-23
申请号：US12892199
申请日：2010-09-28
申请人： SHUENN-GI LEE , CHUNG HSUAN WANG , WERN-HO SHEEN
发明人： SHUENN-GI LEE , CHUNG HSUAN WANG , WERN-HO SHEEN
IPC分类号： H03M13/05 , G06F11/08
CPC分类号： H03M13/2739 , H03M13/2764 , H03M13/2775
摘要： An address generation apparatus for quadratic permutation polynomial (QPP) interleaver receives several configurable parameters and uses a plurality of QPP units to compute and outputs a plurality of interleaving addresses according to a QPP function Π(i)=(f1i+f2i2) mod k, where f1 and f2 are QPP coefficients, k is information block length of an input sequence, 0≦i≦k−1, and mod is a modulus operation. Each of the plurality of QPP units is a parallel computation unit, and outputs in parallel a corresponding group of interleaver addresses, where Π(i) is also a ith interleaving address generated by the apparatus.
摘要翻译：二次置换多项式（QPP）交织器的地址生成装置接收多个可配置参数，并使用多个QPP单元根据QPP函数＆Pgr计算并输出多个交织地址;（i）=（f1i + f2i2）mod k ，其中f1和f2是QPP系数，k是输入序列的信息块长度，0＆nlE; i＆nlE; k-1，mod是模运算。多个QPP单元中的每一个是并行计算单元，并且并行地输出相应的交织器地址组，其中＆amp;（i）也是由该设备生成的第i个交织地址。

87. 发明申请

US20110307673A1 RECONFIGURABLE INTERLEAVER HAVING RECONFIGURABLE COUNTERS 有权
标题翻译：具有可重构计数器的可重新配置的交换机
公开(公告)号：US20110307673A1
公开(公告)日：2011-12-15
申请号：US13157085
申请日：2011-06-09
申请人： Nur Engin
发明人： Nur Engin
IPC分类号： G06F12/06
CPC分类号： H03M13/2789 , H03M13/271 , H03M13/2725 , H03M13/2739 , H03M13/276 , H03M13/2764 , H03M13/2771 , H03M13/2775 , H03M13/6519 , H03M13/6525
摘要： A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver comprises a plurality of reconfigurable counters. The number of values that the counters count is configurable as are their start values. The interleaver further comprises a plurality of memory in which the counters indicate memory positions so that values may be retrieved. Computational elements compute an interleaved sequence of addresses in dependency on the retrieved values. By reconfiguring the counters and possibly changing the content of the memories, the interleaver may be configured for a different interleaving pattern.
摘要翻译：提供可重构交错器，其被配置为产生可配置用于至少两个不同交织模式的交错地址序列。可重配置交织器包括多个可重配置计数器。计数器计数的值的数量可以是其起始值。交织器还包括多个存储器，其中计数器指示存储器位置，从而可以检索值。计算元素根据检索到的值计算交织的地址序列。通过重新配置计数器并且可能改变存储器的内容，交织器可以被配置为不同的交织模式。

88. 发明申请

US20110075615A1 RECURSIVE REALIZATION OF POLYNOMIAL PERMUTATION INTERLEAVING 有权
标题翻译：多元实时交互的实现
公开(公告)号：US20110075615A1
公开(公告)日：2011-03-31
申请号：US12571319
申请日：2009-09-30
申请人： Hanfang Pan , Michael A. Howard , Yongbin Wei , Michael A. Kongelf
发明人： Hanfang Pan , Michael A. Howard , Yongbin Wei , Michael A. Kongelf
IPC分类号： H04W4/00 , G06F1/16
CPC分类号： H03M13/2775 , H03M13/2739 , H03M13/2764 , H03M13/6502 , H03M13/6505 , H03M13/6525
摘要： Systems and methodologies are described that facilitate automatically generating interleaved addresses during turbo decoding. An efficient recursive technique can be employed in which layers of nested loops enable the computation of a polynomial and a modular function given interleaved parameters “a” and “b” from a look up table. With the recursive technique, interleaved addresses can be generated, one interleaved address per clock cycle which can maintain turbo decoding performance.
摘要翻译：描述了在turbo解码期间便于自动生成交错地址的系统和方法。可以采用一种有效的递归技术，其中嵌套循环层能够计算多项式和从查询表给出交织参数“a”和“b”的模块化函数。使用递归技术，可以产生交织地址，每个时钟周期的一个交织地址可以保持turbo解码性能。

89. 发明授权

US07873800B2 Address generator for an interleaver memory and a deinterleaver memory 有权
标题翻译：用于交织器存储器和解交织器存储器的地址生成器
公开(公告)号：US07873800B2
公开(公告)日：2011-01-18
申请号：US10598714
申请日：2005-03-03
申请人： Anders Berkeman
发明人： Anders Berkeman
IPC分类号： G06F12/00
CPC分类号： H03M13/2764 , H03M13/271 , H03M13/2742 , H03M13/275 , H03M13/276
摘要： Method and device for generating an address value for addressing an interleaver memory. Consecutive address fragments to which a most significant bit(s) is to be appended are generated. Only a fraction of the address fragments generated, which potentially will exceed a maximum allowable value, is compared to the maximum allowable value. If the compared address fragment exceeds the maximum allowable value it is discarded. If the compared address fragment does not exceed the maximum allowable value it is accepted.
摘要翻译：用于生成用于寻址交织器存储器的地址值的方法和装置。生成要附加最高有效位的连续地址片段。生成的地址片段的一部分，潜在地将超过最大允许值，与最大允许值进行比较。如果比较的地址片段超过最大允许值，则它被丢弃。如果比较的地址片段不超过最大允许值，则被接受。

90. 发明申请

US20100064197A1 RANDOM-ACCESS MULTI-DIRECTIONAL CDMA2000 TURBO CODE INTERLEAVER 失效
标题翻译：随机访问多方向CDMA2000 TURBO代码交互
公开(公告)号：US20100064197A1
公开(公告)日：2010-03-11
申请号：US12399938
申请日：2009-03-07
申请人： Steven J. Halter
发明人： Steven J. Halter
IPC分类号： H03M13/00
CPC分类号： H03M13/2957 , H03M13/271 , H03M13/275 , H03M13/2764 , H03M13/2771 , H03M13/2789
摘要： An interleaver that implements the LCS turbo interleaver algorithm utilized by the CDMA2000 standard is described. The interleaver includes a first computation unit for receiving an input address and computing a first sequential interleaved address during a first clock cycle in response thereto. A second computation unit is included for receiving an input address and computing a second sequential interleaved address during the first clock cycle in response thereto. The interleaver further includes a comparator for determining whether the first or the second sequential interleaved address is invalid and generating a signal in response thereto. The output of the comparator provides a control signal to a switch which selects the first or the second sequential interleaved address as an output interleaved address for the first clock cycle. The interleaver is further designed to move in a forward direction or a reverse direction.
摘要翻译：描述了实现CDMA2000标准使用的LCS turbo交织器算法的交织器。交织器包括第一计算单元，用于接收输入地址，并响应于此在第一时钟周期期间计算第一顺序交错地址。包括第二计算单元，用于接收输入地址，并响应于此在第一时钟周期期间计算第二顺序交错地址。交织器还包括比较器，用于确定第一或第二顺序交错地址是否无效并且响应于此产生信号。比较器的输出向开关选择第一或第二顺序交错地址作为第一时钟周期的输出交错地址的控制信号。交织器被进一步设计成沿正向或相反方向移动。

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