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81. 发明申请

US20160248444A1 TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF 审中-公开
公开(公告)号：US20160248444A1
公开(公告)日：2016-08-25
申请号：US15053038
申请日：2016-02-25
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Kyung-joong KIM , Se-ho MYUNG , Hong-sil JEONG
IPC分类号： H03M13/27 , H03M13/00 , H04L1/00 , H03M13/11
CPC分类号： H03M13/2792 , H03M13/1102 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2778 , H03M13/2906 , H03M13/3761 , H03M13/3769 , H03M13/616 , H03M13/618 , H03M13/6356 , H03M13/6362 , H04L1/0041 , H04L1/0045 , H04L1/0057 , H04L1/0065 , H04L1/0067 , H04L1/0068 , H04L1/0071 , H04L27/36
摘要： A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to perform parity-permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern; a puncturer configured to puncture some of the parity-permutated parity bits; and an additional parity generator configured to select at least some of the punctured parity bits to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern, wherein the first pattern determines parity bits to remain after the puncturing and then to be transmitted in the current frame.

82. 发明申请

US20160241269A1 BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 4/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 有权
标题翻译：用于低密度奇偶校验的位交换机检查长度为16200，编码速率为4/15和256符号映射，以及使用相同的位交互方法
公开(公告)号：US20160241269A1
公开(公告)日：2016-08-18
申请号：US14718839
申请日：2015-05-21
申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
发明人： Sung-Ik PARK , Sun-Hyoung KWON , Bo-Mi LIM , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
IPC分类号： H03M13/27 , H03M13/11
CPC分类号： H03M13/1165 , H03M13/255 , H03M13/2778
摘要： A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
摘要翻译：本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。比特交织器包括第一存储器，处理器和第二存储器。第一存储器存储长度为16200且码率为4/15的低密度奇偶校验（LDPC）码字。处理器通过基于比特组交织LDPC码字来产生交错码字。位组的大小对应于LDPC码字的并行因子。第二存储器将交织的码字提供给用于256符号映射的调制器。

83. 发明申请

US20160218746A1 BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 2/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 有权
标题翻译：用于低密度奇偶校验的位交换机检查长度为16200，编码速率为2/15和64符号映射，以及使用相同的位交互方法
公开(公告)号：US20160218746A1
公开(公告)日：2016-07-28
申请号：US14718013
申请日：2015-05-20
申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
发明人： Sung-Ik PARK , Sun-Hyoung KWON , Bo-Mi LIM , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
IPC分类号： H03M13/27 , H04L1/00 , H03M13/11
CPC分类号： H03M13/2767 , H03M13/1165 , H03M13/255 , H03M13/2778 , H03M13/2792 , H04L1/0057 , H04L1/0071 , H04L2001/0093
摘要： A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
摘要翻译：本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。比特交织器包括第一存储器，处理器和第二存储器。第一存储器存储长度为16200且码率为2/15的低密度奇偶校验（LDPC）码字。处理器通过基于比特组交织LDPC码字来产生交错码字。位组的大小对应于LDPC码字的并行因子。第二存储器将交织的码字提供给用于64符号映射的调制器。

84. 发明申请

US20160204802A1 Low-Power Low Density Parity Check Decoding 有权
标题翻译：低功耗低密度奇偶校验解码
公开(公告)号：US20160204802A1
公开(公告)日：2016-07-14
申请号：US15075255
申请日：2016-03-21
申请人： Maxlinear, Inc.
发明人： Mingrui Zhu , Curtis Ling , Timothy Gallagher
IPC分类号： H03M13/11
CPC分类号： H03M13/1114 , H03M13/1111 , H03M13/1125 , H03M13/1128 , H03M13/1131 , H03M13/1137 , H03M13/114 , H03M13/1165 , H03M13/616 , H03M13/6505 , H04L1/0045
摘要： In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node.
摘要翻译：在本公开的示例实现中，在低位奇偶校验（LDPC）解码器的消息传送期间，在第一比特组解码期间，可以在第一可变节点达到确定阈值的比特值概率时锁定第一可变节点并且在连接到第一校验节点被锁定的所有变量节点上锁定第一校验节点。所述LDPC解码器可以在所述LDPC解码器的所有可变节点被锁定，所述LDPC解码器的所有校验节点被锁定，达到最大迭代次数或达到超时之后，停止解码所述第一组位。在第一可变节点被锁定的第一组比特的解码的特定迭代期间，LDPC解码器可以避免为锁定的第一可变节点生成比特值概率。

85. 发明申请

US20160192026A1 APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS 有权
公开(公告)号：US20160192026A1
公开(公告)日：2016-06-30
申请号：US14908826
申请日：2014-08-01
申请人： LG ELECTRONICS INC.
发明人： Sangchul MOON , Woosuk KO , Sungryong HONG , Jinwoo KIM , Jongwoong SHIN
IPC分类号： H04N21/61 , H04N21/2362 , H04N21/438 , H04N21/2383 , H04N21/414 , H04N21/434 , H04N21/236 , H04N21/2381
CPC分类号： H04L1/0057 , H03M13/036 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/271 , H03M13/2778 , H04L1/0041 , H04L1/0045 , H04L1/0061 , H04L1/0071 , H04L27/2605 , H04L27/2627 , H04L27/2649 , H04L2001/0093 , H04N21/23614 , H04N21/2362 , H04N21/2381 , H04N21/2383 , H04N21/41407 , H04N21/4345 , H04N21/4381 , H04N21/4382 , H04N21/6131
摘要： The present invention provides an apparatus of transmitting broadcast signals, the apparatus including, an encoder for encoding service data, a frame builder for building at least one signal frame by mapping the encoded service data, a modulator for modulating data in the built at least one signal frame by an Orthogonal Frequency Division Multiplexing, OFDM, scheme and a transmitter for transmitting the broadcast signals having the modulated data.

86. 发明申请

US20160173135A1 TRANSMITTER AND SIGNAL PROCESSING METHOD THEREOF 审中-公开
标题翻译：发射机和信号处理方法
公开(公告)号：US20160173135A1
公开(公告)日：2016-06-16
申请号：US14962077
申请日：2015-12-08
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Se-ho MYUNG , Kyung-joong KIM , Hong-sil JEONG
IPC分类号： H03M13/27 , H03M13/00 , H04L1/00 , H03M13/11
CPC分类号： H04L1/0041 , H03M13/036 , H03M13/1165 , H03M13/255 , H03M13/27 , H04L1/0057 , H04L1/0071 , H04L2001/0093
摘要： A transmitter is provided, which includes: an encoder configured to generate a low density parity check (LDPC) codeword comprising information word bits, first parity bits and second parity bits based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a constellation mapper configured to map the interleaved LDPC codeword on constellation points, wherein the first parity bits are generated based on one of parity submatrices constituting the parity check matrix and the second parity bits are generated based on another of the parity submatrices constituting the parity check matrix.
摘要翻译：提供了一种发射机，其包括：编码器，被配置为基于奇偶校验矩阵生成包括信息字比特，第一奇偶校验位和第二奇偶校验位的低密度奇偶校验（LDPC）码字; 配置为交织所述LDPC码字的交织器; 以及星座映射器，被配置为在星座点上映射交织的LDPC码字，其中基于构成奇偶校验矩阵的奇偶校验子矩阵中的一个生成第一奇偶校验位，并且基于构成奇偶校验的奇偶校验子矩阵中的另一个生成第二奇偶校验位检查矩阵。

87. 发明申请

US20160164709A1 APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS 有权
公开(公告)号：US20160164709A1
公开(公告)日：2016-06-09
申请号：US14962719
申请日：2015-12-08
申请人： LG Electronics Inc.
发明人： Jinwoo KIM , Jongwoong SHIN , Woosuk KO , Jaeho HWANG , Sungryong HONG
IPC分类号： H04L27/26 , H04L29/08 , H04L1/00
CPC分类号： H04L27/2602 , H03M13/1102 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/271 , H03M13/2778 , H03M13/2906 , H03M13/6356 , H03M13/6362 , H04H20/72 , H04H60/07 , H04L1/0041 , H04L1/0042 , H04L1/0045 , H04L1/0057 , H04L1/0058 , H04L1/0071 , H04L5/0007 , H04L5/0048 , H04L5/0053 , H04L27/2627 , H04L27/2649 , H04L69/324 , H04L2001/0093
摘要： A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals, the apparatus comprises an encoder for encoding service data corresponding to each of a plurality of data transmission path, wherein each of the data transmission path carries at least one service component for broadcast services, an encoder for encoding signaling data, wherein the signaling data includes static data and dynamic data, a frame builder for building signal frames, wherein each of signal frames includes the encoded service data and the encoded signaling data, wherein each of signal frames belongs to one of the broadcast services, wherein the static data remain constant in the signal frames belonging to the broadcast service in a duration of a super frame and the dynamic data changes by the signal frames, a modulator for modulating the signal frames by an OFDM (Orthogonal Frequency Division Multiplex) scheme and a transmitter for transmitting the broadcast signals carrying the modulated signal frames.

88. 发明授权

US09363042B2 Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals 有权
标题翻译：用于发送广播信号的装置，用于接收广播信号的装置，用于发送广播信号的方法和用于接收广播信号的方法
公开(公告)号：US09363042B2
公开(公告)日：2016-06-07
申请号：US14728205
申请日：2015-06-02
申请人： LG ELECTRONICS INC.
发明人： Jongseob Baek , Woosuk Ko , Seoyoung Back , Sungryong Hong
IPC分类号： H04K1/10 , H04L1/00 , H04B1/04 , H04L27/26 , H04B7/04 , H04L5/00 , H04L12/18
CPC分类号： H04L1/0071 , H03M13/00 , H03M13/1165 , H03M13/152 , H03M13/159 , H03M13/253 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2721 , H03M13/2778 , H03M13/2906 , H03M13/6356 , H03M13/655 , H03M13/6552 , H04B1/04 , H04B7/0413 , H04L1/0041 , H04L1/0057 , H04L1/0059 , H04L1/0065 , H04L1/0075 , H04L5/0007 , H04L12/18 , H04L27/2601 , H04L27/2626 , H04L27/2627 , H04L2001/0093
摘要： A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for receiving broadcast signals, the apparatus comprises a receiver to receive the broadcast signals, a demodulator to demodulate the received broadcast signals by an OFDM (Orthogonal Frequency Division Multiplex) scheme, a frame parser to parse at least one signal frame from the demodulated broadcast signals, wherein a signal frame includes service data corresponding to each of a plurality of physical paths, a time deinterleaver to time deinterleave service data in the at least one signal frame, a decoder to decode the time deinterleaved service data.
摘要翻译：公开了一种用于发送广播信号的方法和装置。用于接收广播信号的装置，该装置包括接收广播信号的接收机，解调器，以通过OFDM（正交频分复用）方案解调所接收的广播信号;帧解析器，用于从解调的广播信号，其中信号帧包括对应于多个物理路径中的每一个的服务数据，在至少一个信号帧中对时间解交织服务数据的时间去交织器，解码时间解交织服务数据的解码器。

89. 发明授权

US09319072B2 Parallel bit interleaver 有权
公开(公告)号：US09319072B2
公开(公告)日：2016-04-19
申请号：US14804466
申请日：2015-07-21
申请人： Panasonic Corporation
发明人： Mihail Petrov
IPC分类号： H03M13/00 , G06F11/00 , H03M13/27 , H03M13/11 , H03M13/25 , H03M13/29 , H03M13/35 , H04L1/00 , H04L1/06
CPC分类号： H03M13/2792 , H03M13/1134 , H03M13/1142 , H03M13/1154 , H03M13/116 , H03M13/1165 , H03M13/1168 , H03M13/255 , H03M13/27 , H03M13/271 , H03M13/2778 , H03M13/2957 , H03M13/356 , H03M13/6325 , H03M13/6552 , H03M13/6555 , H04L1/0058 , H04L1/0606 , H04L1/0618
摘要： A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.

90. 发明申请

US20160094245A1 LDPC DECODER WITH EFFICIENT CIRCULAR SHIFTERS 有权
标题翻译：具有有效圆形透镜的LDPC解码器
公开(公告)号：US20160094245A1
公开(公告)日：2016-03-31
申请号：US14499284
申请日：2014-09-29
申请人： APPLE INC.
发明人： Asaf Landau , Tomer Ish-Shalom , Yonathan Tate
IPC分类号： H03M13/11 , H03M13/00
CPC分类号： H03M13/116 , H03M13/1102 , H03M13/1111 , H03M13/1137 , H03M13/1165 , H03M13/15 , H03M13/271 , H03M13/616 , H03M13/6552 , H03M13/6555 , H04L1/0057
摘要： A decoder includes variable-node circuitry, check-node circuitry and a Message Passing (MP) module, which includes multiple configurable partial cyclic shifters that each supports only a partial subset of shift values out of a full range of shift values 0 . . . L−1. The variable-node circuitry and check-node circuitry are configured to exchange messages with one another in accordance with a parity check matrix that represents a respective Quasi-Cyclic (QC)-Low Density Parity Check (LDPC) Error Correcting Code (ECC) and that includes L-by-L sub-matrices, and to process the exchanged messages to decode a given code word that was encoded using the QC-LDPC ECC. The MP module is configured to schedule the variable-node circuitry and check-node circuitry that are interconnected in accordance with a respective sub-matrix to exchange L messages simultaneously by assigning a given partial cyclic shifter to shift the L messages cyclically a number of positions that depends on a structure of the respective sub-matrix.
摘要翻译：解码器包括可变节点电路，校验节点电路和消息传递（MP）模块，消息传递（MP）模块包括多个可配置的部分循环移位器，每个移位器仅支持移位值0的全范围内的移位值的部分子集。。。 L-1。可变节点电路和校验节点电路被配置为根据表示相应的准循环（QC） - 低密度奇偶校验（LDPC）纠错码（ECC）的奇偶校验矩阵和彼此之间的交换消息其包括L乘L子矩阵，并处理所交换的消息以解码使用QC-LDPC ECC编码的给定码字。 MP模块被配置为根据相应的子矩阵来调度互连的可变节点电路和校验节点电路，以通过分配给定的部分循环移位器来周期性地移动L个消息来同时交换L个消息这取决于相应子矩阵的结构。

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