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81. 发明授权

US06198308B1 Circuit for dynamic switching of a buffer threshold 失效
标题翻译：用于动态切换缓冲区阈值的电路
公开(公告)号：US06198308B1
公开(公告)日：2001-03-06
申请号：US09281465
申请日：1999-03-30
申请人： David P. Morrill
发明人： David P. Morrill
IPC分类号： H03K190175
CPC分类号： H03K19/01707 , H03K19/0027
摘要： A buffer circuit for providing dynamic threshold control. The buffer circuit includes a pair of input inverters designed with different skewed threshold potential characteristics. The outputs of the skewed inverters are directed to a logic circuit designed to select either the faster or the slower signal received from the two inverters for transmission to passgate devices coupled to the respective inverters. Only one of the passgate devices is enabled to ensure that only one of the output signals from the two inverters is propagated through the buffer. A latch is preferably connected between the logic circuit and the two passgate devices to maintain the states of the inverters and the logic circuit. The circuit can be designed to define the threshold potential at which switching will occur so as to reduce propagation delay or increase it as desired. It is therefore possible using the circuit to increase transmission rates with minimal affect on signal noise.
摘要翻译：一种用于提供动态阈值控制的缓冲电路。缓冲电路包括一对具有不同偏斜阈值电位特性的输入反相器。偏斜反相器的输出被引导到逻辑电路，逻辑电路设计成选择从两个反相器接收的更快或更慢的信号，以传输到耦合到各个反相器的通道器件。只有一个通道器件能够确保来自两个反相器的输出信号中只有一个通过缓冲器传播。锁存器优选地连接在逻辑电路和两个通路器件之间，以保持反相器和逻辑电路的状态。该电路可以设计成限定将发生切换的阈值电位，以便减少传播延迟或者根据需要增加延迟。因此，使用电路可以以最小的对信号噪声的影响来增加传输速率。

82. 发明授权

US06194945B1 Dual threshold digital receiver with large noise margin 失效
标题翻译：双阈值数字接收机具有较大的噪声容限
公开(公告)号：US06194945B1
公开(公告)日：2001-02-27
申请号：US08551981
申请日：1995-11-02
申请人： Hamid Bahramzadeh
发明人： Hamid Bahramzadeh
IPC分类号： H03K1920
CPC分类号： H03K19/0027
摘要： A receiver circuit has a high threshold of 3.3÷2 volts and maximum noise margin. This is achieved by making two transistors in the receiver have channel resistances, under the condition whereas input line carries 3.3÷2 volts and a control line carries 0 volts, that generate an output signal as a first resistance ratio which when multiplied by a supply voltage equals 3.3÷2 volts. Further, the receiver also has a low threshold of 2.5÷2 volts and maximum noise margin. This is achieved by making the above two transistors, plus two other transistors in the receiver, have respective channel resistances under the condition where the input line carries 2.5÷2 volts and the control signal line carries 3.3 volts, that generate the output signal as a second resistance ratio which when multiplied by the supply voltage again equals 3.3÷2 volts.
摘要翻译：接收器电路具有3.3÷2伏的高阈值和最大噪声容限。这通过使接收器中的两个晶体管在该条件下具有沟道电阻来实现，而输入线承载3.3÷2伏，并且控制线承载0伏特，其产生作为第一电阻比的输出信号，该电阻比在乘以电源电压等于3.3÷2伏。此外，接收机还具有2.5÷2伏特的低阈值和最大噪声容限。这是通过在输入线路承载2.5÷2伏特，控制信号线载有3.3伏特的条件下，通过使上述两个晶体管加上接收器中的另外两个晶体管具有相应的沟道电阻，其产生输出信号为当与电源电压相乘时的第二电阻比再次等于3.3÷2伏。

83. 发明授权

US6157236A Parametric tuning of an integrated circuit after fabrication 失效
公开(公告)号：US6157236A
公开(公告)日：2000-12-05
申请号：US927237
申请日：1997-09-11
申请人： Sathyanandan Rajivan , Raoul B. Salem
发明人： Sathyanandan Rajivan , Raoul B. Salem
IPC分类号： H03K19/0175 , G01R31/30 , G01R31/317 , H03K5/00 , H03K19/00 , H03K19/0185 , H03K19/0948 , H03K19/173 , H03H11/26
CPC分类号： G01R31/30 , H03K19/0005 , H03K19/0027 , H03K19/018585 , H03K19/1731 , G01R31/31702 , H03K2005/00071
摘要： The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller. In turn, the tuning controller generates corresponding tuning pattern signals enabling target circuit(s) to changeably tune the target parameter by selectively enabling different tunable portions of the target circuit. For example, by selecting the appropriate load resistance and/or capacitance of the tunable circuit, the rise/fall time of the target circuit is tuned for compatibility with respect to the other portions of the IC or system. The tunable circuit of the present invention advantageously lends itself to post-fabrication correction of design or fabrication problems, thereby increasing the potential yield rate. In addition, the tunable circuit can be tested under different operating conditions in a non-destructive manner without the need for another time-consuming and costly IC fabrication cycle. Other advantages include the ability to selectively operate target circuit(s) of the IC at a higher speed under ideal conditions and at a lower speed under hostile conditions.

84. 发明授权

US6040610A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US6040610A
公开(公告)日：2000-03-21
申请号：US56632
申请日：1998-04-08
申请人： Mitsuhiro Noguchi , Yukihito Oowaki
发明人： Mitsuhiro Noguchi , Yukihito Oowaki
IPC分类号： H01L27/04 , G11C11/408 , H01L21/822 , H01L21/8238 , H01L27/092 , H01L29/78 , H03K19/0944 , H01L29/72
CPC分类号： H01L27/092 , H01L21/8238 , H03K19/0027
摘要： A semiconductor device comprises a chip including a MISFET having a source and a drain, in which one of the source and the drain is connected to a second current supply node, an impedance element having a first terminal connected to the other of the source and the drain and a second terminal connected to a first current supply node, and a switching element, in which a well or a body electrode of the MISFET has an active state and a standby state, and is connected to a bias voltage generator for generating different voltages through the switching element, the threshold voltage V.sub.ths during standby state of the MISFET is higher than the threshold voltage V.sub.tha during active state of the MISFET, a voltage applied to a gate of the MISFET being able to take two stationary values, and the following relationship is satisfied V.sub.DD (1-V.sub.ths /V.sub.DD)
摘要翻译：半导体器件包括芯片，其包括具有源极和漏极的MISFET，源极和漏极中的一个连接到第二电流源节点，阻抗元件具有连接到源极的另一个的第一端子和漏极和连接到第一电流源节点的第二端子，以及开关元件，其中MISFET的阱或体电极具有活动状态和待机状态，并且连接到用于产生不同电压的偏置电压发生器通过开关元件，MISFET的待机状态期间的阈值电压Vths高于MISFET的有效状态期间的阈值电压Vtha，施加到MISFET的栅极的电压能够采取两个稳定值，并且具有以下关系满足VDD（1-Vths / VDD）

85. 发明授权

US5990521A Semiconductor device and method of producing the same 失效
公开(公告)号：US5990521A
公开(公告)日：1999-11-23
申请号：US694938
申请日：1996-08-09
申请人： Tadahiko Horiuchi
发明人： Tadahiko Horiuchi
IPC分类号： H01L29/47 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L27/06 , H01L27/092 , H01L27/108 , H01L29/872 , H01L27/02 , H01L29/48
CPC分类号： H01L27/0928 , H01L27/0629 , H03K19/0027
摘要： A semiconductor device of the present invention is a semiconductor device of a complementary MIS field effect transistor, wherein an anode of a first diode is connected to a silicon substrate of a first conduction type while a cathode of the first diode is connected to a first power supply while a cathode of a second diode is connected to a well of the other conduction type and an anode of the second diode is connected to a second power supply.

86. 发明授权

US5874851A Semiconductor integrated circuit having controllable threshold level 失效
标题翻译：具有可控阈值电平的半导体集成电路
公开(公告)号：US5874851A
公开(公告)日：1999-02-23
申请号：US692595
申请日：1996-08-06
申请人： Tetsuyoshi Shiota
发明人： Tetsuyoshi Shiota
IPC分类号： H01L21/8238 , G05F3/24 , G11C5/14 , G11C11/408 , H01L27/088 , H01L27/092 , H03K17/04 , H03K17/30 , H03K19/00 , H03K19/0175 , H03K19/094 , H03K19/0948 , G05F1/10 , H01L27/04 , H03K17/687
CPC分类号： H03K19/0027 , G05F3/247 , G11C5/146 , H01L27/088 , H03K2217/0018
摘要： A semiconductor circuit includes an internal circuit of plural transistors formed in a well of semiconductor substrate and, for each transistor, a threshold level indicator voltage generating circuit which detects a threshold level of the respective one of the plurality of transistors, a control signal generating circuit which generates a control signal in accordance with the threshold level detected by the threshold level indicator voltage generating circuit and a switching circuit responsive to a received control signal for switching to a designated one of plural power supplies of respective, different voltages for connection to the well. The switching circuit is controlled in accordance with the detected threshold level, so that the well is connected to an appropriate power supply. Any variation in the threshold level thereby is corrected since the well potential is controlled to a proper level so that a desired threshold level is obtained, for each of the plural transistors.
摘要翻译：半导体电路包括形成在半导体衬底的阱中的多个晶体管的内部电路，并且对于每个晶体管，阈值电平指示器电压产生电路检测多个晶体管中的相应一个晶体管的阈值电平;控制信号发生电路其产生根据由阈值电平指示电压产生电路检测的阈值电平的控制信号和响应于接收到的控制信号的开关电路，用于切换到用于连接到阱的各个不同电压的多个电源中的指定的一个电源。根据检测到的阈值电平来控制开关电路，使得阱连接到适当的电源。因此，由于阱电位被控制到适当的电平以便为多个晶体管中的每一个获得期望的阈值电平，所以校正了阈值电平的任何变化。

87. 发明授权

US5739713A Deconvolution input buffer compensating for capacitance of a switch matrix of a high density programmable logic device 失效
标题翻译：解卷积输入缓冲器补偿高密度可编程逻辑器件的开关矩阵的电容
公开(公告)号：US5739713A
公开(公告)日：1998-04-14
申请号：US574776
申请日：1995-12-19
申请人： Bradley A. Sharpe-Geisler
发明人： Bradley A. Sharpe-Geisler
IPC分类号： H03K19/00 , H03K19/003 , H03K17/16
CPC分类号： H03K19/0027 , H03K19/00323
摘要： A buffer which provides compensation for the RC time delay introduced by a switch matrix of a high density programmable logic device (PLD). The buffer includes circuitry to provide an input threshold which varies to compensate for the RC delay of the switch matrix on a high to low input signal transition. The buffer further includes a negative hysteresis circuit to prevent oscillations on slow rate low to high input signal transitions.
摘要翻译：一种缓冲器，其提供由高密度可编程逻辑器件（PLD）的开关矩阵引入的RC时间延迟的补偿。缓冲器包括用于提供输入阈值的电路，其变化以补偿在高到低输入信号转换时开关矩阵的RC延迟。该缓冲器还包括一个负的滞后电路，以防止在慢速率低到高输入信号转换时的振荡。

88. 发明授权

US5654664A Input buffer circuit for a semiconductor memory 失效
标题翻译：用于半导体存储器的输入缓冲电路
公开(公告)号：US5654664A
公开(公告)日：1997-08-05
申请号：US623083
申请日：1996-03-28
申请人： Jong-Hoon Park , Jae-Woon Kim
发明人： Jong-Hoon Park , Jae-Woon Kim
IPC分类号： G11C11/417 , G11C11/407 , G11C11/409 , G11C11/413 , H03K19/00 , H03K19/0175 , H03K19/0185 , H03K19/0948 , H01J19/82
CPC分类号： H03K19/0027
摘要： An input buffer circuit of a semiconductor memory capable of controlling a logic threshold voltage of the circuit according to a change in an external supply voltage, which includes an external supply voltage detecting unit for dividing the external supply voltage into a plurality of regions by comparing a plurality of voltages, which have been divided by different ratios of the entire external supply voltage, with a standard voltage; and a converting unit including a pull-up circuit and a pull-down circuit, for converting input signals of TTL level into signals of CMOS level, according to the regions of the external supply voltage obtained by the external supply voltage detecting unit. The input buffer has an advantage in that margins for a logical high input range and logical low input range are improved when converting voltages of TTL level into voltages of CMOS level, by controlling the logic threshold voltage so as to lower the logic threshold voltage when the external supply voltage level is high and raise the logic threshold voltage when the external supply voltage level is low.
摘要翻译：一种半导体存储器的输入缓冲电路，其能够根据外部电源电压的变化来控制电路的逻辑阈值电压，该外部电源电压包括外部电源电压检测单元，用于将外部电源电压分为多个区域，已经将整个外部电源电压的不同比例除以多个电压与标准电压; 以及包括上拉电路和下拉电路的转换单元，用于根据由外部电源电压检测单元获得的外部电源电压的区域将TTL电平的输入信号转换成CMOS电平的信号。输入缓冲器的优点在于，当通过控制逻辑阈值电压将TTL电平的电压转换成CMOS电平的电压来改善逻辑高输入范围和逻辑低输入范围的裕度，从而当逻辑门限电压外部电源电压高，外部电源电压低时提高逻辑门限电压。

89. 发明授权

US5644266A Dynamic threshold voltage scheme for low voltage CMOS inverter 失效
标题翻译：低压CMOS逆变器的动态阈值电压方案
公开(公告)号：US5644266A
公开(公告)日：1997-07-01
申请号：US559201
申请日：1995-11-13
申请人： Ming-Jer Chen , Chuang-Hen Yang
发明人： Ming-Jer Chen , Chuang-Hen Yang
IPC分类号： H03K19/00 , H03K19/017 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/0027 , H03K19/0013 , H03K19/01707 , H03K2217/0018
摘要： The present invention utilizes a CMOS (complementary metal-oxide-semiconductor) inverter, which includes a PMOS transistor and an NMOS transistor connected in cascade, and back-gate biasing circuits. The back-gate biasing circuit consists of capacitors and loads (active load or passive load). By providing a bias voltage to either one of bulks of the transistors or both of them, the constituted CMOS inverter demonstrates higher operation speed and lower standby current than the conventional one.
摘要翻译：本发明使用包括PMOS串联连接的PMOS晶体管和NMOS晶体管的CMOS（互补金属氧化物半导体）逆变器和背栅极偏置电路。背栅极偏置电路由电容器和负载（有源负载或被动负载）组成。通过向晶体管或其两者的体积中的任一个提供偏置电压，构成的CMOS反相器表现出比常规CMOS反相器更高的操作速度和更低的待机电流。

90. 发明授权

US5589783A Variable input threshold adjustment 失效
标题翻译：可变输入阈值调整
公开(公告)号：US5589783A
公开(公告)日：1996-12-31
申请号：US282177
申请日：1994-07-29
申请人： David C. McClure
发明人： David C. McClure
IPC分类号： H03K19/00 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/018585 , H03K19/0027
摘要： According to the present invention, an integrated circuit device is capable of responding to more than one input threshold voltage level by making only minimal changes to the device. The input buffer of the integrated circuit device is modified to be a programmable buffer that is controlled by a control input signal which may be generated by several different control means. Such control means include a bond option, a mask option, a fuse option, a register option, and a voltage detector option.
摘要翻译：根据本发明，集成电路器件能够通过对器件进行最小的改变来响应多于一个的输入阈值电压电平。集成电路装置的输入缓冲器被修改为可由可由若干不同控制装置产生的控制输入信号控制的可编程缓冲器。这种控制装置包括接合选项，掩模选项，熔丝选项，寄存器选项和电压检测器选项。

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